Design Of ESD Protection For The Output Stage Of PDP Driver IC

This paper focuses on the research of esd protection for the output stage of PDP driver IC, it belongs to the range of high voltage design. During the process of production and test, the IC is easy to be damaged by the ESD, and the ESD ability of the HV devices is weak, so design of ESD protection is very important. The paper focuses on three aspects.First of all, we design and simulation four devices, then give them to the foundry,and we test them with the TLP machine. From the TLP results, we found that the TLP test and the MEDICI simulation are similar and the device LIGBT has the best ESD ability whose HBM can be above 6KV. What’s more, there is a problem between the ESD ability and latch_up immunity.Secondly, we try to change one of the LIGBT’s parameter to improve its ESD’s ability. The main idea is to short the path of discharging the current, so the resistance is lower and there is less power, the device will survive for a more current. While it’s not solve the problem completely.Thirdly, the main idea of this design is selectly triggering the SCR or PNP, this idea solve the problem completely. The detail design idea is to select the SCR or PNP with a switch. The switch is made of LVNMOS, and the design come up with many other plans to make the idea true. According to the simulation, the idea almost becomes true, but it still need to be tape out and test.According to the above what we talk about, the LIGBT has the best ESD ability and the new idea of selectly triggering the SCR or PNP is best to trade off the problem between the ESD and latch_up.