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The Design And Realization Of Physical Layer In 10G EPON Protocol Analyzer

Posted on:2016-04-09Degree:MasterType:Thesis
Country:ChinaCandidate:Y P ZhuFull Text:PDF
GTID:2308330473955035Subject:Optical engineering
Abstract/Summary:PDF Full Text Request
Due to its excellent passive characteristics, passive optical network(PON) has become an attractive scheme to construct low-cost, high bandwidth, low-energy consumption optical access networks. The rapid development of PON technologies results into the coexistence of different PON technologies. As a candidate for the next PON generation, 10 G EPON not only has excellent compatibility with the existing 1G EPON, but also can greatly improve the uplink and downlink bandwidth efficiency, in a cost-effective manner. To conveniently analyze the various PON messages, a protocol analyzer, capable to support multiple PON protocols, are proposed and constructed to our knowledge. In this thesis, the in-depth investigation and examination are undertaken for 10 G EPON application scenario.This thesis focuses on the content of physical layer function in 10 G EPON protocol analyzer. The main works of this thesis are listed below: 1)The current 10 G EPON and corresponding protocols, common interfaces and key techniques are discussed and analysed detailly. 2)According to the required functionalities of protocol analyzer, the schematics are desgned and transferred into a practical circuit board. In this thesis, the designs of power supply, clock and chips are descripted detailly. Additionally, an adaptive GUI software, capable of providing the real-time dynamic analysis and display for the multi-PONs messages, is designed and programmed. 3)According to the standard IEEE 802.3av protocol, the transceiving terminals of 10 G EPON have therotically studied and simulated. 4)An experimental testing platform is built under 10 G EPON communication scenario and used to explore the performances of the uplink and downlink transmission modules, such as synchronization modules, descrambling modules and 64B/66 B decoding modules. Finally, a model machine of the designed FPGA-based 10 G EPON protocol analyzer is successfully produced with the 10 G EPON uplink and downlink packet reception functions, and cooperating with GUI software in the PC, the received messages can be correctly parsed.In this thesis, we do the experiment in the 10 G EPON protocol analyzer system. The analyzer receives the messages of the OLT and ONU at the same time, then processes the received date and sends the obtained message to GUI software in the PC for further analysis and research. The experimental results show that the receiving function and the performance of the whole system meet the requirements of IEEE 802.3av standard. The softwares and hardwares of proposed 10 G EPON protocol analyzer have excellent practicability and expansibility, which has important significance for the engineering application and scientific research.
Keywords/Search Tags:10G EPON, FPGA, physical layer, protocol analyzer
PDF Full Text Request
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