The Design Of Video Acquisition And High-Speed Storage System

With the rapid development of multimedia communication technology, the quality of video image transmission and rate all had great improved. The transmission rate, reliability and distance of the traditional video image collection and transmission technology can’t meet the needs of today. On the other hand, the structure characteristics of traditional mechanical hard disk data storage technology determines its defects, such as capacity, access speed, reliability, which make it become more and more difficult to meet the needs of real-time data storage of today. All of these are becoming great challenges for high-speed video image acquisition and real-time high speed data storage.Camera Link is a kind of the applications of video images and communication interface technology. Because of the adoption of an LVDS transmission and serial communication technology, it has a big advantage on transmission rate, power consumption and transmission reliability. In this paper, on the basis of detailed introduction Camera Link technology, a high speed video image data acquisition system will be realized. The acquisition system is given priority to with FPGA controller, and the LVDS signal will be converted to TTL/CMOS signal by using a dedicated conversion chip.Nand Flash storage technology was based on Flash memory storage technology. With high access speed, large capacity and the advantages of the vibration, it has been widely used in many aspects, especially in mobile devices. At the beginning of this paper, we will introduce Nand Flash chip internal storage structure, interface definition, the detailed timing of the various operations and so on. Then, this paper puts forward a kind of based on Nand Flash multistage pipeline storage structure. The structure can make full use of the chip parallel operation characteristics of the die, chip and bus with limited resources, but a high-speed data access.Then, this paper takes a FPGA as the master control core to implement the parallel storage system controller design. In the controller, based on Nand Flash chip manual control sequence and operating command, the control logic generate the control sequence of read and write pages and erase operations. Because of adoption of MLC Nand Flash chip technology, a higher probability of bit inversion phenomenon will happen. In order to guarante the reliability of data storage, a checking mechanism called ECC calibration algorithm is a must. This paper introduces the principle of ECC check and then completed the hardware implementation of ECC calibration algorithm.At the end of the paper, FPGA simulation is introduced of the controller for storage of writing, reading pages and erasing operations. Through the simulation, the controller can accurately generate control sequence of the Nand Flash.