Technical Resear On SAR ADC Based On 40nm

Successive Approximation Register(SAR) ADC has the characteristics of simple structure and saving power consumption. So with the decreasing of the process dimension, the SAR ADC gradually shows two advantages compared with other ADC structures(for example, the pipelined ADC):(1) most of the circuit for SAR ADC is digital, since digital circuit can operate faster at the level of deep sub-micron and nanometer technology.(2) SAR ADC does not require a high gain and high bandwidth of an op-amp to obtain enough linearity. An op-amp of a high-performance not only costs larger power consumption, but also limited by the short channel effects and the power supply voltage. The advantages of the SAR ADC gradually draw the favor of the designers in the field of low voltage and low power application.In this thesis, a deep research and analysis on the system structure and the key unit of SAR ADC circuit is made based on 40 nm CMOS technology, and a 12 bits 1 MS/s of the SAR ADC is designed.First of all, in order to obtain a better system structure, some factors influencing the performance of the system is analyzed, mainly including capacitor mismatch, block structure, parasitic capacitance, etc. According to the results of analysis and derivation, the whole difference tri-level structure for the basic framework of DAC is selected. According to the unit capacitance and mismatch relationship provided by the vendors, modeling on the DAC by MATLAB is completed.Appropriate unit capacitance and piecewise structure is selected to reduce the value of the sampling capacitance and power consumption while meeting the accuracy requirement,Then, the bootstrap switching of gate voltage, dynamic comparator and sequential control circuits are mainly studied in this thesis. Using traditional latch comparator is difficult to achieve desired accuracy for the 12 bits ADC. While dynamic comparator doesn’t need a bias circuit or has any static power consumption compared with the traditional static comparator. Therefore, a two-stage dynamic comparator is selected. The first stage is a dynamic preamplifier, and the secondary stage is a latch. This thesis mainly analyzes the factors affecting the noise of the dynamic comparator, and analyzes the method of reducing the noise of the dynamic comparator.Finally, the STI effect and WEP effect under deep sub-micron and nanometer technology is analyzed, and the ways to solve the STI effect and WEP effect in the circuit and layout are discussed. Each key circuit unit and the realization of the overall layout of the SAR ADC is completed based on the 40 nm CMOS process, and the post-layout for the 12 bits 1 MS/s SAR ADC is validated. The result of the post-layout simulation shows that at a sampling frequency of 1 MHz, and an input signal frequency of 456 k Hz, the Signal to Noise and Distortion Ratio(SNDR) is 73.77 d B, Spurious Free Dynamic Range(SFDR) is 81.99 d B, and Effective Number of Bits(ENOB) is 11.96. In addition, the power consumption is only 0.67 m W, and the area of the layout is 0.169 mm2.