The Design And Implemention Of 3.52GHz Low Jitter Frequency Source

Being the core of the electronic system, frequency source, namely frequency synthesizer, is an important equipment that determining the performance of electronic systems. With the development and progress of electronic systems, modern communication systems, such as, satellite, radar, navigation, and etc. require much higher performance to the frequency source.According to the requirement of 60 GHz communication system, this thesis gives a high quality frequency source which provides the sampling clock for analog to digital conversion(ADC) circuit in the digital baseband signal processing system. Our task is to design a 3.52 GHz low jitter frequency source to meet the requirements of the communication system. At the same time, this kind of design method also provides a good reference value for the design of local oscillator in transceiver of communication systems.Firstly, this thesis introduces the frequency synthesis technology and its development history, main technical index of frequency source, basic knowledge of jitter, and current research status at home and abroad. Secondly, it introduces the concept, the basic principle of phase locked loop and the building blocks such as: reference source, the phase detector, a loop filter(active loop filter which is composed of operational amplifier and passive loop filter) and voltage controlled oscillator(VCO). And we analyze the noise contribution of each module in PLL in detail. Then we give the system index, and focus on the analysis of the index and derive the relationship among jitter, phase noise and frequency. And we conclude that jitter remains unchanged if frequency is doubled. Then according to the requirements of index, it is derived out phase noise template meeting the needs of the system design. According to the phase noise template, we go on the device selection and determine the best loop bandwidth. And we put forward an active loop filter consisting of a transistor instead of the traditional operational amplifier, which has simple structure, little additional noise. Finally this thesis introduces a specific solution including schematic diagram of the simulation design, PCB layout design and the circuit debugging process meeting the requirement of 100 fs jitter.Then this thesis focuses on the design and implementation of VCO in a PLL, majoring at 620 MHZ low phase noise VCO module design. This thesis introduces the basic theory of VCO and traditional design method, and analyze the basic principle of a new nonlinear method in detail including normalized drive level, the conduction angle, the relationship between noise with conduction angle, and the relationship between the conduction angle with feedback capacitance C2. And we give the specific design and simulation and under the traditional structure and improved output structure. Actual measured phase noise is ? 111.47dBc/Hz at 10 KHz offset and ? 108.19 dBc/Hz at 10 KHz offset.We first propose the basic principle about the design of low phase noise dual-core VCO, namely two active circuitry compensating for a common resonator, and we give the specific design of low phase noise dual-core VCO under traditional output structure and improved output structure, and compare phase noise of each single-core VCO with that of dual-core VCO to verify the validity of the proposed approach. Under the traditional output structure and improved output structure, actual measured phase noise are ?115.47dBc/Hz at 10 kHz offset and ?111.82 dBc/Hz at 10 kHz offset.