The Design Of A 16-bits Dual Slope Integrating Analog-to-digital Converter

With the advancement of technology, demand for high-precision systems has become much higher over the years. Calibration is an essential process to improve the accuracy of such systems, but it requires a series of complex circuitries to be added in order for the systems to possess the calibration capabilities. These may include large amounts of pins, switches, resistors, capacitors, hardware and software. To solve the problem, this thesis proposes a novel method that employs a dual slope integrating ADC to replace the complex circuitries in the calibration system.In this novel method, the dual slope integrating ADC converts an input DC signal to n bits internal digital signals, and these digital signals are thus taken as the calibration signals. In this way, it makes the architecture simple and easy to be implemented with much lesser components and pins. The number of bits that can be used as the calibration signals depends on the resolution of the ADC, and this in turns depends on the accuracy of the front-end integrating amplifier and the switching timing of the charging and discharging cycle. However, the integrating amplifier suffers from offset and noise. The offset is caused by the mismatching of devices and the process variation, and the noise is caused by the resistors noise and the inherent amplifier noise. In order to minimize the offset and noise, the integrating amplifier is designed using a differential structure, and the input buffer amplifier is implemented with self-biased method. On the other hand, to accurately control the charging and discharging timing using transistor-level design is very difficult. Therefore, the design of the digital control module is realized using Verilog code instead, which can imposed various timing constraints on critical timing paths.The proposed techniques are applied to the design of a 16-bit dual slope integrating ADC using conventional 0.25μm CMOS technology. Simulation results show that the offset and noise of the integrating amplifier is 7μV and level of n V respectively, while the offset of the input buffer amplifier is 5μV. With a clock frequency of 1MHz, a reference voltage of 2V and a DC input voltage of 0.5V, the simulated conversion time is 81.86 ms, the digital output is 4000(Hexadecimal).