Design Of A8-channel12-bit Successive Approximation Analog-to-Digital IP Core

Most signals in the nature are analog such as light, heat, voice, magnetic. In order to be detecting and managing by the digital device like the computer, the analog signal in continuous on time must be translate into discrete digital signal. Analog to digital converter (ADC) is the module to realize this function. Successive approximation register analog to digital converter is widely used in many fields such as the industrial control, data acquisition system, portable instrument and consumer electronics because it has some good characters, such as low power consumption, small circuit scale, simple structure and easily implemented.The thesis firstly research the structure and working principle of the Successive approximation register analog to digital converter(SAR ADC), then design a high-speed and precision SAR ADC on the base. SAR ADC contains three modules: DAC module, comparer module and digital control module. DAC module use charge proportional distribution, and the big capacitance is designed by paralleling unit capacity, improving the matching degree. The NMOS switch is replaced by the CMOS transport gate, and resolving the problem of channel charge injection. The comparer use the preamplifier-latch structure, achieved the bandwidth and gain request. Design of the Digital control module use the full-custom method, enhanced the flexibility. After detailed analyzing the design difficulties of eliminating the offset voltage, the thesis use the input offset voltage and the output offset voltage to eliminate the offset voltage.According to the design objective, a12Bits,5operating voltage,50Ksps ADC is designed. Concrete structure is realized and simulated with the specter soft in the cadence environment, and based on the SMIC0.18um technology, the paper complete the AD-IP layout design. The results of the simulation show that the converter can worked with1MHz, reached0.4mV resolution, offset voltage is only6pV, reduced the input reference noise to0.922nV, and chip area is250um×250um, meeting the design requirements.