The Design Of A Frequency Synthesizer Based On JESD204B Protocol

By combining several operations, such as frequency multiplication, frequency division and frequency mixing, the frequency synthesizer can obtain the desired signals. It is now widely used in all kinds of communication equipment and electronic products. In all kinds of these structures, the charge pump phase-locked-loop(CPPLL) frequency synthesizer has the advantages of simple structure and high performance, the frequency signal it produced is very stable and accurate, which can be used as a stable and reliable signal source for the system. At the same time, the phase-locked-loop frequency synthesizer can also produce signals of a plurality of different frequency values, furthermore, the voltage controlled oscillator(VCO) of the CPPLL employs ring-VCO, so the occupied area is small and can be easily integrated onto a chip. Nowadays, with the rapid development of communication technology, communication system requires a low phase noise, narrow channel step, high output frequency and faster response time and so on, therefore, as an important signal source part in the communication system, designing a CPPLL frequency synthesizer with a high performance will face more and more challenges.This CPPLL frequency synthesizer is designed in this paper is based on the JESD204 B protocol, according to the system requirements, it needs to generate 4 phases, 1GHz differential clock signals, and a 100 MHz system clock signal. This design uses SMIC 0.13μm CMOS 1P8 M technology, the whole chip works under 1.2V voltage, and the chip area is 0.122 mm, the current is 22 mA, the system can lock in 5 ?s and output clock signals that satisfy the system requirement, according to the chip test, the period clock jitter is 78.15 ps.