Design And Research Of High-speed OTP Memory

With the fast-speed development of computer and communication technology, the safety in information transportation has become more and more important. As the main medium of data interchange and information storage, memories with higher reliable performance accounts for a larger proportion in chip system. The OTP memory is a kind of the one-time programmable read-only memory. That means the memory coulde be programmed only once. Once the cell is programmed, the date would be inside the memory for ever. It has the advantage of non-volatility, high reliability, high stability, high security, and strong anti-interference ability. Therefore it has been widely used in the field of high confidentiality requirements and complex environment occasions, such as key memory chips,RFID and space military.This thesis aims to design an OTP memory of 64 Kbit with high reading speed and anticipating performance. The design process includes memory cell design, peripheral circuit design and simulation, layout design, tape-out, packaging and testing. At first, I introduced the breakdown theory of the anti-fuse structure we used and analyze the working mechanism of the memory cell. Then elaborate the read-write circuits design and simulation of OTP memory. The design of multi-dimension and multi-level decoders has the access to a random disposition of memory array and will reduce the delay of signal transmission time in the same time; the two-stage charge pump circuits in the program system control the internal gerneration of high-voltage without damaging adjacent cells. The structure of sensitive amplifier in read-out circuits is simple and the addition of two stage latch is to ensure stable and reliable exported data. In addition, the reading speed determines the OTP memory working speed. By adjusting the parameters of the key device through read-out channel, we can achieve different access-time and realize the design of high-speed OTP memory requirements. During the layout design process, the paper emphasizes on the solutions to some special problems. Then run the chip level post-layout simulation with Fine Sim EDA software. If the simulation results show that the circuit has problems, we find the reasons, modify circuit and return to the layout. Then do the post simulation again, repeate the process until the simulation results is right. After that, extract the GDSII date and tapeout.Finally, test the chip’s function and parameter after tape-out, the shortest access time is 45 ns, means the fastest frequency is 22.2MHz. The test results show that the chip works properly and achieves the design specifications.