The DFT For DSP And Testing Method Research

The subject of this dissertation is the research on the design for testability in the design environment of System on a Chip. The original test methods mostly used the functional test vectors to test the integrated circuits. The difficulty of testing system chip goes beyond the people's imagination. Test issue of the chip turns into the bottle neck of the development of IC .Considering The above reasons, the author consults a wide range of documents about DFT design , does a good research theoretically and practically. The test system of a DSP chip has been studied and designAimed at the system testing control model, the test access state machine which is defined by IEEE 1149.1 standard is as kernel logic. Mean while,IEEE 1149.1 has the scalable ability so special test instruction and data registers are added based on IEEEP 1500,this purpose is to achieve the different test ways to different models. Boundary scan aims at the application system. we detailed presents the design of the boundary scan which is in accordance with IEEE 1149.1. This structure can save the I/O ports of the chip and simplify the testing program; we also discuss the internal full-scan, it is advanced for the difficulty of the fixing state of circuit. According to the real conditions of the fixed-point DSP chip, we use the full-scan which is based on mux. It is achieved the high fault coverage with little impact on the chip.Since the chip has interior SRAM and it's difficult and slow to test exteriorly of SRAM, so in chapter four we use the technique of BIST in design of testability of SRAM. It is possible to test the memory at normal working speed.The research of this paper can meet the test requirement of DSP by computer simulation and guarantee its normal work. Meantime, the Design-for-Test of embedded chip may gain some experience from it...