Design And Implementation Of A High Precision Pulse Generator

Digital pulse width modulation(DPWM) is to generate a digital pulse signal with microprocessor, DSP or FPGA, its width can be adjusted. Because of the flexibility of programmable control and little influence by the environment, it has become a basic method in digital control and power conversion. Pulse width precision directly affects the output voltage and current accuracy of the digital control and power conversion performance. However, with the development of electronic technology, the system requirements more frequency and accuracy of control signal, the precision of digital pulse width is limited by the clock frequency, in order to meet the demand for high-precision pulse in the digital control and power conversion, so, research and implement of high-precision pulse waveform generating is become more and more necessary.In this paper, for the demand of high-precision pulse waveform generating, we have proposed a new method based on Altera cyclone III family FPGA to achieve high-precision digital pulse waveform generation. It takes advantage of the PLL reconfiguration technology to dynamically produce a fine phase offset and the counter to produce a coarse pulse width, the coarse pulse width plus the fine offset can implement fine adjustment of the pulse width, finally output the satisfied pulse waveform, increase pulse width resolution up to 125 ps.The main contents are as follows:1. Studied the necessity and the methods to improve the resolution of a digital pulse width in current. Discussed the methods of using DSP, ASIC, FPGA to implement pulse waveform generation, combine with the design requirements, and finally decided to take advantage of the PLL reconfiguration to generate high-precision pulse waveform based on FPGA.2. Discussed the theory and the main methods to controll the rise time and fall time in current.Finally decided to adopt the pulse edge controll method based on the charging capacitor array to regulate the pulse edge time.3. Synthesis the frequency of pulse based on the DDS + PLL + counter architecture, the frequency resolution of pulse is determined by the DDS clock frequency resolution, and completed the relevant hardware circuit design.4. Wrote each module during the digital pulse generation and controling modules of FPGA peripheral circuits by verilog hardware description language, applied the frequency and phase of PLL reconfiguration to achieve pulse width modulation with high accuracy, and the digital pulse waveform is generated.5. Developed the testing plan according to the design specifications, wrote the pulse driver, tested circuit functions and analyzed of the test results.