The Design Of Dealy Locked Loop For DPWM

In recent years,demand for dc-dc converters that operate in high switching speed,low voltage with high power efficiency has become very high.Traditional power converter is easy to be affected by environment,and difficult to improve resolution.However,the digital dc-dc converter realizes the control of the output by sampling the output voltage,compensating in the digital domain,and then converts the digital duty ratio into PWM wave through the digital pulse width modulation(DPWM)circuit.Compared with analog power,digital power has the characteristics of high resolution,few peripheral components and little environmental impact.As an important part of the digital dc-dc converter,DPWM provides the output of the digital control feedback loop.Its performance determines the quality of the digital dc-dc converter.Therefore,the DPWM structure in the digital dc-dc converter requires relatively high resolution.In this paper,the basic principle of DPWM is studied.Then,the relationship between DPWM and limit cycle is analyzed,and some stability criteria are given.Many DPWM architectures are proposed,such as counter-based,delay line,sigma-delta and jitter.In order to achieve high resolution,the counter-based type needs high clock frequency.Delay line is easily affected by process.Sigma-delta type increases the complexity of the structure,and consumes a large chip area.The jitter DPWM brings low frequency ripple noise to the system and reduces the response speed.To solve the problem of traditional DPWM structures,the working principle of delay-locked loop is studied,and a DPWM based on delay-locked loop is proposed,and the voltage comparator is used to replace the voltage-controlled delay line,and high resolution is achieved.In addition,the phase frequency detector adds three NAND gates and three NOR gates to the conventional structure,and is used to generate different switch control signals under the control of digital signals.The charge pump circuit adds a voltage replica circuit that prevents charge sharing.The two loop filters match the locks of the different pulse widths of the odd and even periods,respectively.The delayed-locked loop is locked at 10 ns pulse width in odd cycles and 20 ns pulse width in even cycles,and provide reference voltage and reference current for PWM module.The reference current charges the capacitor and generates a ramp voltage.PWM is realized by comparing the ramp voltage with different reference voltage.The circuit was designed and simulated in Cadence using a 0.18?m CMOS process.The simulation results show that the common narrow pulse width of the phase frequency detector is 2 ns.The charge and discharge current of the charge pump is 5?A,and the relative deviation is-0.70% ~ +0.31%.The adjustment range of the output voltage Vres in the loop filter 1 is 160 m V to 400 m V.The adjustment range of the output current Icap in the loop filter 2 is 0 ?A to 30 ?A.DPWM has a resolution of 625 ps and has good linearity and stability.