Design And Application Of DPWM Based On Dichotomy Of Calibration Mechanism

The power management chip was widely used in electronic products. Traditional power management IC was mainly implemented by anolog circuits. But, there were so many disadvantages of the analog circuits such as easy to aging, poor portability, not easy to be integrated which made the applications of anolog power IC in the high-end market limited. Digital power supply with its high integration, strong portability and high accuracy in the lower output voltage, wide range of load and various power management and other high-end market cut a striking figure. This study would be aiming at the digital power supply to expand. As all we know, the digital Proportional Integral Differential(DPID) and Digital Pulse Width Modulator(DPWM) were the two most important modules in digital power. DPID was used to compensate the system, so as to guarantee the system stable, DPWM was used to transform the duty cycle information of the DPID code into a square wave signal. Therefore, effective compensation network and of high precision, high linearity DPWM is critical on digital power system stability.This paper optimized the DPID Verilog code, and the burr produced by the traditional DPID module was eliminated. In addition, this paper also proposed a DPWM based on the Hybrid DPWM(HDPWM) with the dichotomy of calibration mechanism. This introduced algorithm guaranteed the delay line of every two adjacent delay unit getting the same information, so as to improve the linearity of DPWM effectively. This paper introduced in detail the design method of digital DC-DC converter, the basic principle and the discrete domain model first. And then introduces the design of DPID module and DPWM module from front to back. Finally, the the functions of DPWM and digital power supply were verified by the simulation results. With using Synopsys’ s EDA tools, we realized the 9-bit DPWM working at 32 MHz system clock frequency. The DPWM was applied to the digital DC-DC converter with the switching frequency of 2MHz. The DPWM module was implemented in 0.13 μ m CMOS process, and the maximum differential nonlinearity(DNL) was only 0.136 LSB, integral nonlinearity(INL) was 0.15 LSB. In this paper, the final digital DC-DC converter was realized with input voltage range of 2.7V~4.2V and the output voltage o of 0.7V~1.8V.