Study And Design Of Low-Voltage Low-Power Audio Sigma-Delta Modulator Based On130nm CMOS Technology

Duo to the high resolution of Σ△ADC, it is widely applied in the field of audio equipment, measuring instruments, communications and sensors. With the rapid growth of multimedia SOC chip, domestic design of low-power, low-cost, high-precision audio ADC has become an urgent need. Meanwhile, for the sake of extending the standby time and integrate more available modules, this thesis studies and designs a low-power, low-cost Σ△ADC based on audio applications, which has very important practical significance.The latest international trend of Σ△ADC is making use of low-power quantizer for multi-bit quantization in recent years, but quantization noise and the noise caused by non-linear DAC become the major factors affecting the SNDR. This thesis applies several key technologies to depress power dissipation and increase the SNDR. To achieve low consumption, on one hand the modulator operates under low voltage of0.6V, the system adopts feedforward path and multi-bit feedback structure to lower the signal swing in the integral path. Besides, the integrator uses correlated double sampling (CDS) technique to reduce leakage and improve the effective integral gain. On the other hand, this paper firstly proposes the method of digital addition, which avoids the signal attenuation caused by passive summation and consumption with the area issue caused by active summation. These key methods decrease the input and output swing of the op amp, which relaxes its bandwidth and gain requirements, thereby it depresses the power dissipation.In the aspect of improving the SNDR, this design faces the problem that quantization noise and DAC nonlinearity degrade the performance of the modulator. The Σ△modulator in this paper adopts a8-bit successive approximation ADC as the feedforward quantizer to replace traditional Flash ADC. It aims to further improve the quantization depth and reduce the quantization noise. In addition, applying the data weight average (DWA) technique to eliminate the DAC nonlinearity in multi-bit feedback system, it makes the mismatch noise one order shaped and improves the linearity. The digital Truncation technology is adopted for decreasing the logic complexity and consumption of DWA simultaneously. This dissertation designs and realizes a low-voltage low-power high-resolution audio Σ△ADC based on TSMC130nm process. The chip operates under0.6V and the core area is only0.25mm2. Under the condition that the frequency of input signal is12.5kHz with500mV amplitude, and the frequency of sampling signal is800kHz, the measured SNDR reaches77.3dB. The modulator only consumes22μW and its Figure of Merit (FoM) is0.076(pJ/step), which meets the application requirements of audio equipment.