Stack-through Silicon Via Dynamic Power Consumption Optimization In 3D Integrated Circuit

With the continuous development of integrated circuits, increasing integration of each chip, unit device number increases sharply. The increase of the length of the connection between the units not only makes the two-dimensional plane of chip area increases, but also affects the circuit work speed and performance. Hence the theory of three dimensional integrated circuits appears. Three-dimensional integration method can effectively improve the integration of the system at the same time improve the performance of the circuit. Three-dimensional integrated circuit has many interconnection forms, in which Through Silicon Via(TSV) greatly shorten the length of the interconnection and provides a new idea for the three dimensional integrated communication. Based on TSV, this dissertation is mainly concerned with the dynamic power consumption optimization problem and set out to the circuit parameter model. Main content includes the following aspects:1. TSV electrical parameter has been extracted. First of all the manufacturing technology of TSV is introduced, including its process flow and four key technologies. And then different TSV shapes and different fill materials are discussed. So the shape of a TSV and the surrounding full interconnection structure is determined for the follow-up work. On the basis of the structure of the cylindrical TSV a relatively complete circuit parameter of the structure is extracted, including parasitic capacitance and parasitic resistance of TSV, parasitic inductance, parasitic conductance, and the coupling electrical parameters between two TSV and so on.2. TSV dynamic power consumption model has been established. First of all, the importance of power in the circuit performance are illustrated and the typical CMOS process and the composition and the source of power are analyzed. Then, the dynamic power consumption of TSV is calculated and analyzed on the basis of single TSV structure by using the circuit parameters extracted. Also, the effect of the parasitic parameters on the dynamic power consumption is compared. Especially the relationship between the diameter of the TSV and dynamic power consumption is discussed. At the same time, the calculation method of three-dimensional interconnection delay is defined, and the relationship between the diameter of the TSV and delay is analyzed, too.3. An optimization model of multi-layer TSV dynamic power consumption has been established. In view of the dynamic power consumption optimization problem, a new structure of multilayer three-dimensional integrated circuits is proposed. The diameters within the structure reduce step by step so as to reduce the power consumption, under the influence of the delay time and area constraint, finding out the best reduction rule. The result shows that in the model of this paper, dynamic power consumption optimization of TSV is up to 19.52% at the expense of the 5% delay cases.4. Finally, the applicable case for the adopted optimization model is analyzed. The results are compared by changing other parameter of TSV including TSV length, thickness of oxide layer, TSV filling materials or the constraint conditions and so on. Comparison results show different optimization effects of the model under different conditions. Under the actual situation, proper parameters according to the process environment should be chose to get the best optimization effect.