Design And Implementation Of Rate-Compatible LDPC For UAV

With the increasing of UAV and its various tasks and complex environments,the adaptive performance of UAV channel coding is becoming more and more demanding.Especially,the adaptability of short channel channel coding for controlling the forward link of UAVs is a big challenge.Searching for a short-length channel coding that is rate-compatible and easy to achieve in UAVs is the key to solve this problem.In this paper the short-length rate-compatible LDPC codes is adopted to improve the performance of UAV’s rate-compatible strategies while reducing the complexity of its implementation and saving the resources.Since LDPC codes have capacity-approaching performance,rate-compatible LDPC also have an excellent performance.But the high complexity of its implementation and the small range of compatibility shrink its developments.In order to solve this problem a LDPC codes which is rate-compatible and is easy to implement in UAVs is constructed by the improved PEG(Progressive-edge-growth)algorithm and quasi-cyclic construction method in this paper.And the design of the codec,based on this short-length rate-compatible LDPC,is proposed.It is of great value to improve the adaptive performance of UAV channel coding,which can effectively reduce the resource usage in order to meet the requirement of rate compatibleFirstly,this paper summarizes the current and development of rate-compatible LDPC code,the hardware implementation of LDPC codes and the basic theory of LDPC codes.By comparing the advantages and disadvantages of the construction theory of LDPC codes and the analysis of the compatibility methods of code rate-compatibility,a RCE-LDPC code with lower triangular is constructed with the improved PEG algorithm and quasi-cyclic construction method.And this rate-compatible LDPC can achieve 1/2,2/3,3/3,7/8 rate and its code length can be 192 bits,288 bits,384 bits,576 bits.Then,because of the quasi cyclic and the lower triangular structure,an improved encoder architecture based on RAM is proposed with the improvement of LDPC coding algorithm based on FPGA.On the basis of this architecture,an encoder is implemented which can achieved the four rates and length.And a simulation and test on it.Finally,according to the requirements of the code rate and length,and LDPC code decoding algorithm,we treat the min-sum as the decoding algorithm,and design the decoder.In the process of implementation of the decoder,an carry Look-ahead adder tree and shift comparator array are proposed,realized with the four rate and code length decoder and effectively supports high decoding throughput,and completed the simulation test of the decoder.