Design Of Internal Inter-core Communication In The Multicore Processors

Design of PLC processor by building on the Hua-P language architecture based on FPGA which is on the basis of an in-depth study of traditional PLC technology, processor technology, Hua-P language and FPGA proposed. Hua-P language and the ladder is very similar which are readily convertible to each other. Hua-P language has more data manipulation commands. To be able to perform Hua-P language directly, designed Hua-P processor and its instruction set.The thesis completed the functional design of Hua-P processor instruction set design, coding, a detailed description of the design methods of ACTAB instruction and JPTAB instruction in Hua-P instruction, which used in the Verilog programming language to implement on FPGA. Hua-P instruction is compiled and simulated with the Quartus II and Modelsim SE, the results of the simulation is demonstrate and the design is implementation. The section of multiple data operation is the concept of the high efficiency of the processor which belongs to EISC.