On The Divider Realization Of FPGA Algorithm

Traditional integrated circuit design technology has been unable to meet the increasing performance of the whole system requirements. SOC design IP-based, a hierarchical hardware description language for system functions and structure of the main means of description, using a computer as a platform for EDA.Tools Research has indicated that the composition of the IC systems. As the SOC to the integration and overall consideration of the entire system, the design can be in the same technology conditions, the realization of high-performance systems indicators. In addition to the use of the system resources,which is also a programmable device with sufficient resources programmable logic, for the realization of other additional logic.Meanwhile Altera PLD itself in the structural aspects has been the development and innovation.The recent series of Hard Copy Stratix device is a design capacity to deal with, from the prototype design to mass production of a complete solution, in an attempt to become the overall ASIC alternatives. Altera's SOPC development tools, hardware and software design, integrate to provide customers a very good development environment. Altera's Max II has been widely used. Very popular PLD (programmable logic device) design software, it has FPGA and CPLD these PLD applications and promotion, circuit components and embedded system design College and the professional teaching practice and made a very important contribution. It is a continuation of Max II and all the advantages of a more perfect PLD Design Tools. The SOPC Builder design tool is embedded system created a new design concept. This paper presents a platform includingAltera's NIOS II processor, and the internal and external memory unit. Users can also design their own IP peripherals.From the user's point of view, SOPC Builder is capable of producing a complex hardware system tools. Therefore, SOPC Builder can be seen as an IP module for the importation, integrated systems for export tool.In the Altera Nios Embedded Processor, Users can order the NIOS system to increase user-defined instructions, to strengthen its hard real-time software algorithm processing capability. Furthermore, the increase in the user-defined instructions can access the same memory or NIOS systems logic. Using user-defined instructions, users can be a complex sequence of standard instructions, to simplify hardware implementation with a single command.Customized instruction is the use of soft-core Nios embedded processor SOPC system an important characteristic. By hardware module consisting of customized orders through single clock cycle or more clock cycles hardware arithmetic operations to complete the original very complex software task, and not only that, customized orders can also visit Nios memory or outside the system interface logic. Using Nios customized instructions on this characteristic, Nios developers can design dysfunction powerful customized instruction.All four basic computations divider is the most complex. So the division is the most time spent on the operation, but also to achieve the maximum number of different algorithms arithmetic. This chapter uses two types of programs to achieve binary divider to compare their performance, speed and the resource. A linear convergence is the division algorithm, the other is the rapid convergence of the division algorithm. SOPC Builder of the self-definition of eight Convergence divider directive added, and draw conclusions.