| With the development of the modern digital signal processing technology and the development of high-speed signal processing device, complex signal processing in real time becomes possible. In order to deal with the complex electromagnetic environment, radar communication integration system research has very important practical significance. The integration of the receiving system needs to deal with signal detection, signal separation and parameter estimation, signal identification and sorting, etc. Among them, the result of signal separation will become the input of the subsequent signal processing, therefore, measures to effectively isolate high quality signals have important implications for subsequent processing. At the same time, the performance of parameters estimation will provide effective reference on the signal identification. This thesis combines actual project practice with the current theory, mainly studies the signal separation and parameter estimation algorithm on the radar-communication integration system, and put forward some algorithms that are suitable for engineering practice.At first, based on the differences of radar system and communication system, the possibility of integration of the two systems is discussed. Then the thesis studies the characteristics of several communication signals and radar signals in both time domain and frequency domain. Then the thesis focuses on the signal separation and parameter estimation. In the aspect of signal separation, a signal separation algorithm that combines the signal power spectrum analysis and independent component analysis is put forward, effectively balances the separation performance and the cost of time. In terms of parameter estimation, the algorithm mainly deals with the pulse width, pulse amplitude, arrival time, carrier frequency of the radar signals and carrier frequency and symbol rate of the communication signals. The blind estimation algorithm is suitable for most of the signals. Through the simulation, the algorithms achieve good effect. Finally, the algorithms are implemented on a hardware platform of FPGA and DSP and the verification test results on hardware platform are given. |