Development Of An Efficient Tool To Control Analog Circuit Simulation Flow

The operations and performance of System-on-Chip are affected and limited by the performance of analog circuit. Along with the scaling of CMOS technology into the nanometer era, the operations and performance of analog circuit are impacted significantly by the variations of process parameters, power supply voltages and operating temperatures. To verify the operations of analog circuit and assure the accuracy of analog circuit, analog circuit designers have to run abundant PVT (Process-Voltage-Temperature) simulations and Monte Carlo simulations.In practice, there are some problems in analog circuit simulation flow. The post-layout simulations are large-scale, always take long time and produce large data. As the rapid development of semiconductor technology, the parasitic effects in circuit layout seriously affect the performance and lifetime of the circuit. The results of transistor simulation and post-layout simulation could be much different, such as static working points and noise. So designers have to clearly be aware of the difference between two kinds of simulations to debug and adjust schematic and layout.Beside these, a big IC multinational generally has several analog design teams and many analog designers, sharing the limited EDA tool licenses and the hardware resources such as disk space and computer servers.Although ADE tool provided by Cadence is a standard process of analog design flow and widely used in the industry, it has complex interface, and is difficult to set simulation parameters to run batch of simulations. It always takes quite a long time to submit simulation jobs and load result database. Furthermore, it doesn’t provide a method to compare the difference between the results of pre-layout simulation and post-layout simulation.In order to solve these problems in analog PVT simulations and Mento Carlo simulations, an automated tool named fsim is developed in this thesis. Fsim tool which is developed in Perl/Tk language invokes EDA tool Spectre simulator from Cadence, and could be interacted with LSF. It has the flexibility to run all kinds of PVT simulations and Mento Carlo simulations, and even the two nested batch simulations. It also can compare the static working points of the pre-layout simulation and post-layout simulations. Fsim supports all kinds of the technology processes and is easy to maintain and update. Designers can use fsim with graphical interface friendly to submit batch jobs conveniently and efficiently, and finally get an integrated result which is easy to handle. Beside these, designers can also use fsim to properly share the limited simulator license and hardware resources, and monitor the batch simulation jobs’operations in LSF on time.Fsim tool has already been used in analog circuit design work of 4 products in LSI which are taped out successfully, such as read channel product of 28nm process and SERDES product of 65nm process. More than 20 designers have used fsim to solve the problems during analog circuit simulation flow, and improved their work efficiency.