| Nowadays, SoC products are becoming more and more popular, especially mobile phones and tablets. In order to adjust to the increasing market and techniques, the time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. It is a big challenge that SoC product developing is facing.Typical SoC product release cycle usually comprises of two parts, hardware design and software development. And the time spent on software development trends to more and more (over 70% at most). As a result, immediately after the hardware details have been roughly determined, a simulation platform for software development should be provided as soon as possible to develop application and system software of SoC products. Hence, a critical step in shortening product release cycle is providing a fast prototyping of customizable and extensible simulator.Unfortunately, there are several challenges for existing simulation platforms to leverage a fast prototyping for SoC software development. It results from the fact that, on the hardware design side, it has been a common practice to integrate IP (intellectual property) cores or customization ISAs to fact the tight produce release timeline and the increasing hardware complexity. The modularity and high reusability of IP cores can significantly reduce hardware exploration complexity. However, providing simulation support of IP cores or customized instructions is not that easy. First, as an IP core is generally a black box for the sake of intellectual property, there is only functional behavior rather than detailed implementation available, which makes developing a simulator quite time-consuming. Second, due to well-tuned features, more and more IP cores (even more than 100) are integrated into one SoC chip. It is also very time-consuming to understand and then simulate the behaviors of so many IP cores. Third, as there are usually a variant of IP cores with different communication interfaces, communications with these IP cores need to specifically designed. Fourth, extension of new instructions requires changes to the complier tool chain, which is also quite time-consuming.To address these problems, this paper introduces RPSim, an extensible and easy-to-use architectural level full-system simulation platform for SoC software development. We use a hardware and software hybrid mechanism for IP core fast prototyping. The netlist of an IP core is mapped onto FPGA for the simulation of functional behavior and timing information, and a general interface is used to eliminate the differences among different IP cores. Furthermore, a configurable library mechanism is designed for new instruction extension. The accurate register dependency relation is also assured in the meantime to guarantee the accurate timing simulation.In summary, this paper makes the following contributions:A software-hardware hybrid mechanism and an interface for the fast prototyping of IP core simulation.A configurable library mechanism and an interface for the fast prototyping of new instructions without complier tool chain modification.A fast prototyping SoC simulation platform for software development. |
