Research On SoC For WBAN Baseband

As people focus on health problem and the development of semiconductor technology, medical electronics get more and more widely used, which contributes the development of wireless body area network (WBAN). In 2012, IEEE officially released WBAN standard protocol IEEE802.15.6, specify the contents of MAC layer and NarrowBand,UltraWideBand,Human Body Communication physical layer, causing the interest in academia and industry.Physical layer locates at the bottom of OSI reference model, directly faces the transmission medium and provides the physical connection of the original bitstream for MAC layer. WBAN NarrowBand physical layer is low-power physical layer protocol, optimized specifically for medical electronic. This paper carries out in-depth analysis and research on it. Using matlab to do the modeling and simulatation of narrow band physical layer, this paper analyze the the performance of the system under different operating modes. Results show that the system meets the requirements of the standard WBAN protocol.Then PHY hardware accelerator is designed for WBAN narrowband physical layer. As medical electronics have strong requirements on energy, this paper treats power as the primary consideration during PHY module design.Among different designs, this paper prefers the design of low power consumption and low hardware cost. This design time-shares the BCH coding, spreader, interleaver and scrambler module. For filter design, this paper uses canonical signed digital encoding and the way of shared subexpressions to reduce power consumption.Then this paper further research on SoC system for WBAN baseband, include hardware and software platform. In order to reduce power consumption, idle modules automatically enters sleep mode by clock gating cell and are waked up until necessary.To facilitate configuration, simulation and verification of the SoC, this paper use wxPython to implement the graphical configuration interface.Finally, the SoC for WBAN baseband is simulated and verified by FPGA. To evaluate the power and area and compare them with other papers, the PHY hardware accelerator is synthesized, placed and routed.