Research On Low Power Digital Filter For Seismic Exploration System

Petroleum is the most important resource for every country today. The demand for petroleum in China has increased greatly alone with the total GDP number in the past few years. In last year, more than a half of the petroleum consumed in china was imported from outside. In contrast to the increasing number on consume, domestic petroleum production number started to decrease. Petroleum exploration industry must be improved so much that exploration team can find more oilfield, and to decline the petroleum dependence on the outside.In nowadays, it is very hard to find easy-to-exploitation exploration oilfield because of the over-exploitation in the past few decades. But more oilfields in deeper layer or in lithology geological structure have not been detected yet. The cost of exploitation of these oil fields is a great number and they are considered to have limited worth for the industry. Now the situation changes, the cost of exploitation can not compare with the price rising because of the lack of petroleum. The new generation of seismic exploration equipment has to be high resolution and high precision features so that the details of geological structures can be detected. This means people can find oilfield in deeper layer and in special geological structures. These high resolution and high precision seismic exploration equipments has much more acquisition units than normal ones, the number even can reach Three hundred thousand to a million large. As the unit number increase greatly, they power consumption is a very important index of seismic exploration equipment which is used in open wild country environments.The current international mainstream seismic signal filter program has been very mature. It can meet the needs of seismic exploration equipment and is widely used in the order of ten thousand and below the instrument exploration. A lot of achievements of the design of the Seismic exploration equipment have been made in China in recent years. Because the unit number is very large, how to further reduce the chip power consumption by designing a very significant issue.Digital filter is an essential part of acquisition unit in digital seismic exploration equipment. The performance of digital filter directly affects the output indexes such as SNR (Signal-to-Noise Ratio) and THD (total harmonic distortion). The purpose of this paper is to design a new kind of digital filter which have an excellent frequency response for seismic data and low power consumption for equipment.In chapter 1, the basic methods and the principles of seismic exploration are introduced by analyzing seismic exploration equipment. Seismic exploration history and current status of the instrument also be discussed. After that, the role of the digital filter played in seismic exploration equipment is generally discussed.In chapter 2, main content is to analyze seismic exploration instruments and seismic signals and to draw demand for seismic design of digital filter in detail by the analyzing result. At first, the impact of seismic wave formation and Classification of seismic waves are introduced to explain the role of different frequency bands. The result show that seismic digital filter should be high decimation, anti-aliasing, low power and low distortion. The structure of front-end hardware decimation digital filter and back-end software equalization digital filter is put forward.In chapter 3, author put forward the multi-level structure of seismic digital filter by the result in chapter 2. The front-end hardware decimation digital filter is consisting of 5 CIC digital filters and 3 FIR digital filters, and the back-end software equalization digital filter is a high order FIR filter. The main function of front-end hardware decimation digital filter is to get high decimation and anti-aliasing features. The main function of back-end software equalization digital filter is to equalize the non-flat and rippled frequency response pass band of front-end hardware system. Filter parameters of front-end hardware decimation digital filter are calculated by digital filter theory and the constraints on frequency response. Performances of front-end filter are verified by frequency response analyst, sine wave simulation test and impulse responses test. Filter parameters of back-end software equalization digital filter are designed by frequency sampling method for FIR filter. At last, the computation quantity of this design is compared with current mainstream design CS5376A, and the result show that the new design can reduce power computation quantity effectively.In chapter 4, the main target is to realize the front-end hardware decimation digital filter in Verilog language and do some verification work in FPGA. Structures of front-end FIR filters is designed by polyphase decomposition method and realized in DSP algorithm. Multiplication in each FIR filter share only one multiplier and a new realization of multiplier is proposed. The realization of multiplier used a reloadable CSD multiplier structure which can reduce the number of gate reversing for every Multiplication. At last, this design is realized in FPGA and the simulation results show that the project can translate the algorithm into Verilog code exactly. Some hardware resource area estimation work also be accomplished to give some suggestion to further work.Chapter 5 summarizes the main work and ideas in this thesis, compare the new design with current mainstream design CS5376A, and make some conclusions. Bring forward that this design should be realized in ASIC silicon if we want to get lowest power consumption. Expound the Innovation in this thesis and give some directions to further work base on this research.