FPGA System Design For Still Image Coder Based On Intra Prediction

Due to the advances of computer and Internet technologies, still image coding develops rapidly and is used widely. JPEG is a well-known still image coding standard. Compared with JPEG, the latest image coding standard JPEG2000 not only has better coding efficiency but also includes many new features.H.264/AVC intra frame coder with intra prediction is one of the most important technologies in H.264/AVC video coding scheme. It is competitive with JPEG2000 in terms of both coding performance and computation complexity. Thus, H.264/AVC intra frame coder is more attractive for still image coding. However, there is no effective bits controlling scheme which limits the application in transmission adapting limited bandwidth.Firstly, in this paper, a bits constrained control algorithm is proposed for H.264/AVC intra coder. Secondly, a FPGA based hardware system for still image coding adopting intra prediction coding is designed. In the system, two-stage macroblock pipelining is proposed to double the processing speed. A pipelining restart technology is also proposed to maintain the system performance under bits control. Configurable 4-parallel hardware architecture for intra predictor and the interleaved luminance and chrominance prediction schedule are designed to improve the predictor utilization. System also adopts a parallel 4×4 2D DCT transform architecture combined with Hadamard transform. Finally, a CABAC entropy coding architecture is presented including binarizer, context model selector and fully pipelined arithmetic coder. According to the simulation, all units come up to meet expectations of the design.