Real Time Signal Processing Design Of WCDMA Based On FPGA

Modern communication systems rely on the signal processing extensively and raise higher demands of signal processing methods. In recent years, the integrated circuit technology has been developing rapidly, which can integrate much more complicated circuits. Thus it plays a more and more important role in the field of real time signal processing. So far, the FPGA chips are made to meet different needs, such as high ability of signal processing, high ability of transmission, and high flexibility of control. However, the development on FPGA is complicated and skillful. Based on Wideband Code Division Multiple Access(WCDMA) system, how to get faster and more effective signal processing on FPGA is discussed in this dissertation. The author’s major contributions are outlined as follows:1. The overall design and completion on FPGA has been studied. According to the character of real time signal processing, a development process of FPGA design is proposed. Taking WCDMA signal processing on physical layer as an example, PRACH channel processing and PCH channel processing are designed on FPGA, and several commonly used techniques of FPGA overall design are summarized in the end.2. The modularized design and completion on FPGA has been studied. Two modules in WCDMA signal processing are designed, including preamble code searching module and chip code synchronizing module. Several skills in modularized design are summarized in the end.3. The standardized design and completion on FPGA has been studied. Based on the features of real time signal processing and the experiences of FPGA development, the basic principles and commonly used techniques of FPGA design are summarized. Also region constraints of FPGA design using Plan Ahead tool is discussed.4. A test bed of FPGA designs for the system function has been studied. The FPGA system and a computer are connected through Ethernet, in which the data on inner signals are sent to the computer for analyzing.5. The self-testing method on FPGA development system has been studied, and a simple, feasible method is proposed. A test vector generator needs to be added to the FPGA overall design, making sure the correct test of the logic functions inside FPGA without input signals.