Design And Implementation Of Space-time Adaptive Radar Signal Processing Based On FPGA And DSP Architecture

Space-time adaptive processing(STAP)technology was born in 1973.This technology can effectively suppress strong ground(sea)clutter and strong interference in two dimensions of space-time,greatly improving the detection ability of weak low-speed targets of airborne radar.After nearly half a century of development,STAP theory has matured,and the engineering of STAP technology has become the main research direction in this field.With the development of high-performance FPGA and DSP processor technologies,FPGAs are endowed with powerful parallel processing capabilities and DSP with powerful floating-point computing capabilities.The STAP real-time processing system based on FPGA and DSP architecture has become the mainstream today.Based on the above background,this paper focuses on the implementation technology of space-time adaptive processing based on FPGA and DSP architecture.First,the STAP theoretical algorithm is studied,and a complete set of engineered STAP algorithm schemes is given.The scheme is suitable for non-uniform clutter environments and has good clutter suppression performance.The target-oriented constraints and the generalized inner product(GIP)algorithm are used to select the training samples to provide a relatively ideal uniform sample for estimating the clutter covariance matrix,and then the m DT dimensionality reduction algorithm and the subspace projection algorithm are used to uniform samples and non-uniform The sample is subjected to clutter suppression,and finally the two-dimensional CA-CFAR and the two-dimensional OS-CFAR are used to perform constant false alarm detection.Then the radar signal processing platform based on the Open VPX standard is designed for the STAP algorithm scheme.The standardized design is highly versatile and compatible with VPX boards of different manufacturers.The signal processing core of the platform is four signal processing boards based on FPGA and DSP architecture.Its flexible structure is suitable for modular design and powerful computing performance.At the same time,a high-speed interconnection network based on serial Rapid IO is designed so that any Rapid IO device on the platform can communicate with each other.Each link uses 4 channels,the theoretical data bandwidth of a single link reaches 18Gbps,and the data throughput is large.Immediately after the realization of the engineered STAP algorithm on the designed radar signal processing platform,this is also the research focus of this article.This article discusses in detail the implementation process of space-time adaptive processing,including the division and distribution of STAP algorithm modules,FPGA logic design,DSP programming,communication design of FPGA and DSP,especially for improving real-time performance Pipeline design,memory planning and program optimization,as well as fixed-point bit width expansion,normalization or fixed-point to floating-point design to improve accuracy are elaborated.Finally,build a STAP system test platform,use multiple sets of simulated radar echo data to test and analyze the STAP system,including real-time,accuracy error and resource consumption.The test results show that the average processing time of each coherent processing interval is 23.522ms,and the system delay is 62.578ms,which meets the real-time requirements.Compared with MATLAB double-precision floating-point arithmetic,the relative error accuracy of the target detection of the STAP system is on the order of 10^-3.The system computing and storage resource consumption accounts for less than 70%,and there is a certain system expansion space.