Design Of Video Encoder For The Miniaturized Space Camera

With the development and advancement of information technology, video compression plays an irreplaceable role in the real-time video communication of mobiles, internet video streaming and the forefront of space exploration. Based on the rapid upgrade of the programmable logic devices, the video compression system is developing towards high-speed, high-compression, high-reliability and miniaturization. Thus the miniaturized realization of video compression is the current hotspot.Based on the miniaturizing design goal, this paper proposes a new design and implementation of camera’s video coding system. Using the FPGA architecture, the designed system stores the data in the external memory SDRAM. The simple and efficient algorithms are adopted. Based on the pipeline process, the design for reliability can ensure the whole system working in the normal.The paper’s main contents are outlined as follows:Firstly, the paper introduces the research background and development of video coding standards concentrating on the video encoder. The characteristics of each standard are mentioned, especially the widely used MPEG-4 and H.264. And the paper refers to the FPGA application and development in the field of aerospace briefly.Secondly, the basic principles of video coding are described, which adopt the general mixed compression methods including time domain, space domain and code encoding. As well as it introduces the popular framework of video codec and implementation. In detail, the paper contrasts the MPEG-4 and H.264 in technical differences, realizations and modes.Then, the paper elaborates the advantages and disadvantages of the current popular architecture based on comparison. For the space application and the design goal of miniaturization, the encoder design based on FPGA is proposed. On the theoretical foundation of the encoder’s key technology, the FPGA architecture of encoder and realization are explained, including the CMOS sensor control, auto exposure, coding unit processing and compressing the image, and bit stream output. And the encoder uses the pertinent block search algorithm for motion estimation comparing with others. The matching method is SAD. Consideration of hardware resource utilizing, the system realizes the modularization and the pipelining technology and enhances the processing speed.Furthermore, the FPGA system is simulated functionally in Modelsim software and tested on hardware platform. And the results prove that the system performs well in speed and function.