Design And Optimization Of VLD Terminal Of High Voltage VDMOS

In the fast-changing world,although the global power semiconductor market is constantly upgrading,VDMOS has always been one of the main product categories of power devices.For high-voltage VDMOS,a good terminal structure is the key to achieve high withstand voltage.The higher the withstand voltage,the larger the terminal area required,resulting in an increase in cost.VLD(Variation Lateral Doping)with the characteristics of small length and high withstand voltage is commonly used in VDMOS.Compared with the field limiting rings,it has higher chip utilization.However,there is very little information about the specific design methods of VLD terminals in the literature.Based on this,this article conducts optimization and design research on VLD and proposes a universal design method for VLD terminal in high-voltage VDMOS,and the VLD designed by the method can achieves high voltage.The main contents of this article are as follows:1.Based on the theoretical analysis of the withstand voltage principle of the VLD,the formula was used to derive two optimized VLD impurity concentration distribution methods and the specific design methods of the mask are given for the two impurity concentration distribution methods firstly.Simulations have verified that the VLD designed by the two optimization methods can achieve better breakdown voltage compared with the VLD terminal designed by the existing method.In addition,considering the influence of the curvature effect of the terminal chamfer in the layout design,an improved method is also proposed for the layout design of the VLD at the terminal chamfer.Provide theoretical guidance for the design and research of the structure and layout of VLD.2.A 1000 V VDMOS device was designed through Tsuprem4/MEDICI simulation software and L-Edit layout software.The cell structure is a conventional planar vertical structure and the terminal structure is designed by using the VLD design method mentioned above.Compared with the field limit ring,the area of VLD terminal is reduced by 25%,and the withstand voltage can reach more than 90% of the parallel plane junction.After fabricating and testing,the designed wafers achieve the electrical characteristics requirements.And the actual withstand voltage value has a certain margin compared to the withstand voltage requirement.The optimization method of VLD terminal proposed in this paper has been well verified.