Research On Power VDMOS Design And Optimization Methods

Power MOS transistors and power integrated circuits developed faster and faster in recent years.And its application become more and more widely in the areas of the car electronics, inverter, switching power supply, motor speed, high frequency oscillator.It have developed differents variety of structure power VDMOS field-effect transistor in order to satisfy people differents kind of demands,it have super node structure and half super node structure and so on.The new structure VDMOS emergence to improve the breakdown voltage and reduce on resistance of the power VDMOS and improve the performance of the switching frequency of these important indicators.The design of the power VDMOS device mainly about the structure and process, the emergence of the new structure is modified based on the traditional structure of VDMOS, but the development of the power VDMOS in recent years,it new structure just changed a certain performance, and new structure VDMOS manufacturing process is difficult and cost become larger than traditional structure VDMOS.In this paper,on the basis of the traditional power VDMOS structure and from the structure parameters of the device,under different structural parameters and research the changes of the device performance. The research content mainly includes the influence factors of the breakdown voltage and on resistance of device,structure parameters on the influence of longitudinal electric field, the influence factors of parasitic capacitance between the source and drain.(1) The influence factors of breakdown voltage and on resistance:Through changed the epitaxial layer thickness and epitaxial layer doping concentration of VDMOS and simulated breakdown voltage and on resistance changed tendency, in the range of parameter to make the high breakdown voltage and small on resistance of the device.And comparative analysis that get the best design parameters and the optimal design method.(2) The device of the longitudinal electric field:Changed the epitaxial layer thickness, epitaxial layer doping concentration, P-body spacing, P-body junction depth, gate source voltage and source drain voltage of device and simulation the distribution of electric field and the maximum electric field point on the vertical direction changes under different structure size, and get the change law of electric field changed with these parameters.(3) The influence factors of parasitic capacitance between source and drain: Change the epitaxial layer thickness and epitaxial layer doping concentration and gate source voltage,simulated its C-V characteristic curve under the different size, analysis the parasitic capacitance change rule between VDMOS source and drain under the different epitaxial layer thickness and epitaxial layer doping concentration and gate source voltage. In order to increase switching frequency, reduce the parasitic capacitance between source electrode and drain electrode, according to the analysis result get the best design size, optimizing the performance of the device.