Architecture And Microcircuit’s Research Of NoC For QoS

Along with the rapid development of semiconductor chip technology, research’ result of system-on-chip is widely used in various fields of industry.However, because of its kimitations for interconnect structure, the concept of network-on-chip have been proposed by many research’ institutes at home and abroad They have also studied this distributed architecture They also present a variety of modules with the need of network chip area, power consumption, network latency and throughput of special needs My paper is based on the latest proposed multidrop express channels network topology structure,and achieve the goal of rising the network’s performance,it will conduct a detailed study of the key modules,such astopology.deadlock avoid.cache routing and data congestion.First, this paper analyzes the research status of NoC at home and oversea, and not only introduces the parts of the composition of basic theoretical knowledge, common network topology structure, data exchange technology, routing algorithms, deadlock lock or live lock and topology network performance parameters such as elaborate, but also introduces the relevant to the basics theoretical knowledge of QoS on the paper. In this paper, data exchange method is packet switching technology,which divided data package into flit, routing algorithm is XY deterministic routing algorithm.data exchange with cross switch.and cache use virtual channel and fifo.Then this paper proposes an improved multidrop express channels topology of the network Architecture, the improved architecture is easy to be designed and implemented whit low network diameter, low-power, multi-channel etc. and the paper analyzes its working principle of the microcircuit and introduces the implementation of the various components of the module, and the architecture introduces the elastic buffer flow control with the avoiding congestion and deadlock datavia the combined effect of the elastic buffer and virtual channels,it will avoid congestion with the help of excape mechianism and ensure the implementation of flow control and the low priority packe’QoS.It extracts out the resource into the shared regional(SR) where the data of urgent or high prority will be send directly.at last.the data will sand to the router.so it will effectively save hardware consumption and reduce delay.The architecture with the new topology of the network,EB and SR,will achieve the best QoS performance.Finally, this paper uses simulation of modelsim and NS2 simulate data signal for the micro circuit of the topology network structure of QoS, which contrast to the traditional 2Dmesh and Ring for power consumption, throughput and network latency and other network parameters.The paper also displayed through chart.The simulation results show that the Architecture proposed in this paper has greater throughput, saving too much power Consumption.low average delay, but the disadvantage is the complex degree of the overall architecture design and a high degreeof difficult to achieve physical wire. Therefore, this structure is more suitablefor real-time, interactive chip architecture.