Design And Implementation Of New RZ-DPSK Optical Signal Demodulation And Decoding System

Since Chinese British Charles Kao published a paper in 1966, optical fiber communication experienced a rapid development from nothing to boom, low-speed to high-speed, single wave to multi-wave, short-distance to long-distance in the short decades. Optical fiber communication is almost everywhere in today’s communication field, like the internet, telecommunication network and broadcasting network and it is marching on to a higher speed, larger capacity and farther distance.As the continuous development of optical fiber communication, in order to improve optical fiber transmission rate and guarantee transmission quality, the modulation and demodulation techniques which matured sufficiently in wireless communications was used in optical fiber communication. At present, the most commonly used modulation techniques in optical fiber communication are amplitude modulation and phase modulation. Intensity modulation was used widely at the beginning of optical fiber communication. However, as the emergence and expansion of WDM/DWDM networks, the phase modulation is applied broadly. Modulation systems like DPSK and DQPSK are applied successively in optical signals of lOGbps, 40Gbps and even 100Gbps.The main content of this paper is to design and realize a new RZ-DPSK demodulation and decoding system. Unlike the usual RZ-DPSK demodulation system, this system uses SEP+ optical module instead of balanced receiver, realizing the accurate signal demodulation and decoder output. Firstly, the paper elaborates the concept of DPSK phase modulation and demodulation, analyzing the reason why RZ-DPSK is chosen as the common modulation system. Secondly, it introduces the system’s software and hardware modular design principle and working process with the description of each hardware and software modular. Thirdly, this paper emphasizes the optical signal demodulation algorithm that based on digital balance detection. The algorithm avoids the disadvantage that the SEP+ module could not return detection peak level which makes the justification of the delay interferometer more rapid and accurate. This paper also introduces the realization of Berlekamp-Massey iteration-based BCH decoding algorithm in FPGA. The system chooses FPGA chip as the main computation processing chip. Therefore, the algorithm realizes the real-time wire-speed error-correcting decoding function which ean satisfy the data throughput of high speed signals. Lastly, the decoding accuracy, justification time and decoding quality of the delay interferometer as well as the error-correcting function are testified and compared through field tests. The tests prove that both the stability and reliability of the system’s software and hardware are excellent.