Design Of Silicon-based Radio Frequency Power Amplifier For WLAN

Power amplifier is an important component of the RF front-end which will affect the coverage area, signal quality and equipment working time. So the design of high-power, high linearity and high efficiency RF power amplifier has been a popular research field. In the past, high output radio frequency power amplifier design has been based on compound semiconductor process which has a higher power density and higher frequency characteristics, such as GaAs. However, compound semiconductor technology is not compatible with conventional low-cost bulk silicon technology. With the development of SOI CMOS and SiGe BiCMOS process, design of RF power amplifier in silicon process becomes possible. This paper demonstrates two RF power amplifier designs based on SiGe BiCMOS process and SOI CMOS process respectively. The main work and achievements are as follows:Firstly, the performance requirement of power amplifier was analyzed, especially the EVM and spectrum mask requirement for WLAN application. A simulation environment was designed for the EVM test of IEEE 802.11g signal using Ptolemy simulation method. In this simulation environment the relationship between EVM and AM-AM effects was studied and a method to improve the efficiency was proposed. And then, power matching method and gain expansion effect were discussed in details.Secondly, a three stages power amplifier was designed in SiGe BiCMOS process. The characteristics of SiGe HBT device were analyzed and a method to estimate the output power of HBT device was proposed based on Kirk effect. Base stability resistor was used to improve the stability. A load pull method was adopted to figure out the proper output match impendence. In order to enhance the flexibility of matching circuits, bonding wires were chosen to behave as matching inductors. The layout of the chip was designed in Cadence Virtuoso. Measurement results shew that the gain is 26.6 dB and S11 is -16.5 dB at 2.45 GHz and the output power at 1 dB compression point is 23.6 dBm. For IEEE 802.11g 54 Mbps modulated signal, the PA delivered 16.6 dBm power with 5.6% error vector magnitude.Thirdly, a power amplifier applied for WLAN was designed based on IBM 0.18 um SOI CMOS process. To improve the reliability of the circuit, both the driver stage and the output stage of the amplifier are designed using self-adaptive-bias circuit, so the voltage distribution of the common gate MOSFET and the common source gate MOSFET become more balanced. This chip uses two stage cascode structure and is integrated with the input matching circuit and the inter stage matching circuit. The test result shows that the gain of the amplifier is 23.9dB, 1dB compression point is 23.9 dBm, and the PAE is 39.4%. When the test signal is IEEE 802.11g 54 Mbps and the EVM is 3%, the output power reaches 16.3 dBm.In conclusion, this paper demonstrates two power amplifier designs in silicon process, so this work may be some of reference value.