Design Of A Low Noise And High Gain CMOS Operational Amplifier

With the rapid development of the domestic telecommunications industry, operational amplifier(op amp for short) is widely used in various types of high-frequency or intermediate frequency radio receiver pre-amplifier stage and the high sensitivity of electronic devices.In situations of weak signal amplification,noise interference in useful signal for op amp itself may be very serious,and thus designing an op amp circuit with a low noise,high power gain,good stability,sufficient bandwidth and large dynamic range.CMOS analog integrated circuits op amp is the most important element in the circuit.However,MOS field-effect transistor(MOSFET) circuit would bring noise, especially with the MOSFET sizes decreased and the signal amplitude decreased, noise characteristics of the low-frequency of the circuit is becoming increasingly important.Therefore,the paper designs a high-gain low-noise amplifier used for receiver's front end.First of all,analyze main noise sources of op-amp circuit,then design the corresponding component parameters of the circuit considering of the basic noise theory and adjust the parameters of certain components.Op amp input stage used PMOS differential input gain enhances direct telescopic structure to improve gain and suppress noise,the output stage is also the form of differential input to further suppress noise,while using class AB push-pull output forms to improve efficiency and to prevent cross the more distortion.To ensure the stability of common mode output voltage in differential op amp,dual differential pair composed of common-mode feedback architecture is used.Zero and poles existing in the circuit are analyzed and deduced.Miller is composed of MOS linearity of resistance instead of adjustable resistance,which is connected with capacitance compensation circuit in series.Seen from the whole circuit noise performance,the circuit's noise characteristics are optimized.Based on Taiwan Semiconductor Manufacturing Company(TSMC) 0.18μm CMOS process parameters,the whole op amp circuit is designed.Simulation is done by PSPICE simulation software.The results show that:when the supply voltage is 3V,and connected with 5 pF load capacitor and 20 kΩload resistor,the design of CMOS op amp's quiescent power consumption is only 34 mW,time delay is 1.5μs, the measured AC voltage open-loop is 134 dB,the open-loop phase margin is 68°,the unity-gain-bandwidth is 203 MHz.When the frequency is at 10 kHz,the input voltage noise density of the designed operational amplifier is only 3.51nV/Hz^1/2,the performance index has reached the design requirements of low input noise.