IGBT Failure Analysis

Since1960s, the emergence of Power Electronics (PE) technology contributes a lot in increasing the utilization of energy, converting electric power and opening a way for new energy strategy all over the world. Till now, the rapid growth of PE tech helps people to utilize the natural resource properly, efficiently and sustainably.Nowadays, the power devices, such as IGBTs and Power MOSFETs, play as the core of power electronic system. The failure of devices usually results in the damage of the PE system. In order to alleviate the failure risks and increase the utility of power devices, it is necessary to understand the system thoroughly and use the devices properly. In other words, researching on various kinds of failure patterns under different applications will help to understand working principle and damage condition, and also raise the lifttime of devices.During recent years, failure analysis has become a popular research domain in power electronics. By means of various kinds of researching tools, such as371b (static characteristic measurement instrument), SEM, EDX, FIB cutting, TEM and so on, I-V curves of IGBTs were extracted, IGBT bare chips were dissected and failure conditions of devices were analysed. Moreover, advanced plans on device packaging were proposed in correspondance with failure pattern respectively.1. As to gate failure mode, pre-analysis on I-V characteristic was given. Gate-Emitter current leakage path along with failure spots on gate pad were found by THEMOS mini equipment.2. With regards to over-current failure during turn-on and turn-off, IGBT chips were dissected by griding and scribing. In addition, SEM and EDX were used to assess the damage condition. Failure mechanism was studied based on existing papers and was verified by saber simulation3. Concerning static over-current failure, chip dissection was carried out to evaluate the damage situation. Failure machanism was explored, Corresponding verification experiment was carried out via clamped inductance test circuit.4. In case of over-voltage failure condition, chip dissection was carried out to analyse the failure point and damage condition. Failure mechanism was explored based on literature. The failure reason was given via substantial amount of experiments. Lastly, saber simulation was carried out to verify the explanation of experiment results.