Implementation And Structural Optimization Of The LDPC Decoder Based On Cuda Platform

With the development of mobile communications, the concept of SDR(Software Defined Radio) become more and more popular at the beginning of the1990s. However, it requires a very high-speed software and hardware to implement digital signal processing. With the parallel computing capability of GPU, the combination of GPGPU and SDR technology can be a good solution to the problem of real-time processing. In the signal processing of communication, channel decoding often occupy more than half the amount of calculation, so this thesis aim at the design of high-throughput LDPC(Low Density Parity Code) decoder on CUDA(Compute Unified Device Architecture) platform.In this thesis, the design and optimization of high-throughput LDPC decoder are studied form the following four aspects:Firstly, to have the best understanding of the design, the detail of GPGPU architecture and the method of theoretical performance calculation is researched. What’s more, this thesis gives a detailed explanation of CUDA programming model and the communication mechanism.Secondly, a comprehensive research and simulation of BP(Belief Propagation), TDMP(Turbo-decoding Message-passing) algorithm is done for the data of computational performance and the degree of parallism. Through the analysis, TDMP algorithm has the faster convergence rate and lower demand of storage respected to BP algorithm, and the average number of iteration is reduced by20%to50%.Thirdly, the improvement of SISO unit is done for high-speed computing. The calculation of SISO unit is very time consuming, so five different algorithms is chosed to find the quickest version. By the simulation, the most suitable for CUDA platform is chosed in the simulation.Finally, specific to the CUDA platform, the overall design is presented, for example, the programming model mapping. What’s more, the detail of design is also be presented, such as memory access, avoid of the bank conflict and the solution of matrix compress and uncompress.The simulation result is given at the end of thesis to demonstrate the feasibility and efficiency of the decoder. Compared with other researcher’s paper, the decoder shows a better performance.