| In December2013, the Ministry of Industry and Information Technology published TD-LTE licenses to the three major operators officially, marking the arrival of the era of commercial4G. Compared with previous mobile communication systems, TD-LTE has obvious performance advantages. Its downlink peak rate can be comparable to cable broadband network. In addition, LTE network has improved in the cell edge throughput, enhancing the mobile user experience.TD-LTE base station downlink bears terminal’s control information and business data. The number of users and the peak rate that base station can support are affected by cooperative processing of access network whose architecture consists of three layers, especially the performance of signal processing in physical layer plays an important role in it.This paper researches downlink multi-core design based on MSC8157multi-core DSP, and implements on hardware in order to verify the effectiveness and performance of the design. The paper is dedicated in the physical layer, which is at the bottom of three layers architecture of the access network that communicates with layer-three about control and configuration information and with layer-two about sub-frame information, to design the interface about physical layer and high layers. For the internal processing of the physical layer, this paper divides DSP cores into four types according to the function to process downlink parallel, main control core, shared channel core, control channel core, FPGA interface core. The main control core charges with the high layers interface and takes the responsibility of the downlink scheduling. Shared channel core is responsible for the processing of PDSCH. Due to the characteristics of hardware facilities of MSC8157and factors about PDSCH load, multiple DSP cores are divided into shared channel core to complete the processing of PDSCH collaboratively. Control channel core handles with other links besides PDSCH. FPGA interface core delivers OFDM baseband signal in time domain to the FPGA and FPGA will work in collaboration with the front-end module to transmit wireless signal. According to the design scheme to implement downlink in MSC8157, the transmission rate is greater than54.9Mbit/s. |
