Research On The Iterative Synchronization Algorithm For BVR Wireless Communication Systems

MIMO (Multiple Input Multiple Output) communication system using space resources, spatial multiplexing and spatial diversity and other technologies, without increasing the total transmit power and system bandwidth, enhances the utilization of wireless communication system bandwidth, improves system capacity, thus has been widely used in various fields of wireless communication.This paper studies the basics of MIMO communication systems, including the transmitting and receiving technologies, such as space-time coding, capture synchronization and etc. In this pater we introduce our effort on designing and developing hardware-based MIMO communication platform using FPGA, DSP. Then we show our work of realizing and testing Verilog implemented modules on the hardware platform.First, the article looks into the basic theory of MIMO communication systems, including the system model, channel capacity, space-time coding. From the model of the system, we describe the channel capacity of MIMO systems, further analyze the advantages and disadvantages of three space-time codings and finally choose space-time block codes (STBC) which has a simple decoder design and receive the maximum diversity gain. Secondly, from the transmitting and receiving ends, we designed the MIMO platform and analyzed the anti-noise performance of Golay sequences and the way it generates. The transmitting end includes data collection, Turbo coding, QPSK mapping, repeat, STBC, framing, molding filtering, frequency modulation and other modules. We discuss the main principles and implementation of these modules respectively. At the receiving end, the synchronization need to be achieved under larger span SNR. It is achieved by referring to the adaptive door threshold of late gate, early gate, mid-gate, the design of the loop filter, combining the relative threshold and the absolute threshold, adjusting samples with high precision.Then, referring to the system design, we designed hardware MIMO communication platform based on FPGA and DSP. Our work including chip selection, power management, clocks design, the overall interface design, completing all the schematic system and some PCB drawings. Then we carried out a hardware circuit debugging, completing all the debugging of underlying drivers and interfaces, including Rapid I/O, Gigabit Ethernet port, DDR3, etc. After completing the hardware platform on FPGA Verilog-based transceiver end module, we verified the system originating IF spectrum and proved that the receiver can be synchronized at-30db low SNR.