Design Of A Fast IntDCT/IDCT Algorithm And Its Implementation For HEVC Standard

With the development of the multimedia and information technologies, thedemand for higher quality, higer frame rate, higer compression rate of digitalvideo applications are increasing day by day. The previous video coding standardH.264/AVC has shown its limitations, can not solve all kinds of the problems inthe developing process of digital video. So, the Joint Collaborative Team onVideo Coding (JCT-VC) which composed of the VCEG of ITU-T and the MPEGof ISO/IEC developed and launched the next generation high efficiency videocoding (HEVC) standard. The new standard can achieve compression ratedoubled under the same picture quality situation. The HEVC using hybrid videocoding framework, similar to H.264/AVC and adopt many new technologies toimprove coding performance, but increases the complexity of encoding anddecoding device.In order to reduce the high encoding and decoding complexity and enormousamount of calculation, the traditional real value DCT/IDCT are replaced with theinteger DCT/IDCT in the HEVC standard. A fast algorithm for the integerDCT/IDCT based on the properties of the coefficient matrices of integerDCT/IDCT is proposed in this paper. Since the HEVC supports different sizes oftransform units from4×4,8×8,16×16to32×32, thus, the fast algorithms arerequired to calculate the different points one-dimensional (1-D) integerDCT/IDCT. Then this paper presents a reusable high throughput architecture for1-D DCT/IDCT computation, which can be used to compute different points(4/8/16/32) transforms. In hardware design, we take reusable structure and thematrix parity decomposition method into account to decrease the hardwarecomplexity and increase the throughput, meanwhile, the multiplication operationis converted to the shift-add operations to speed up the calculation and reduce thecircuit area. To verify the performance of the designed hardware architecture, thefunctional simulation, the logic synthesis using DC, and the placement androuting using SocEncounter are completed following the Very Large ScaleIntegration (VLSI) design flow. The result shows that the chip area is1724×1714μm2, the operating frequency is80MHz and the throughput is2560×106samplesper second. The design can be used to encode and decode8K video at30FPS.The research will make the integer cosine transform applied more widely indigital video processing and will also promote the development of hardwareencoder and decoder chip for HEVC.