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Research On WCRT Analysis Of Multicore Real-Time Systems With Shared Buses

Posted on:2012-09-28Degree:MasterType:Thesis
Country:ChinaCandidate:Y JinFull Text:PDF
GTID:2298330467477975Subject:Computer software and theory
Abstract/Summary:PDF Full Text Request
It is obvious that multicore processors are increasingly used in embedded real-time systems for high performance and low energy consumption. Although multicore processors provide better average performance, the existing shared resources, accessed by programs in different cores, make the time behaviors of real-time system highly unpredictable. To ensure that the system demanding time is enough, the real-time system is required to analysis the time properties before it starts. The appearance of multicore processors brings an enormous challenge to time analysis of real-time systems.The shared memory bus, which widely exists between processor and caches, different level of caches, as well as processor and external memory, is one of the most critical resources in the multicore system. However, the shared bus may severely affect the timing properties of the multicore real-time system. To solve this above problem, this thesis mainly analyzes the WCRT of the multicore real-time system with the shared buses. We first propose a pseudo-polynomial-complexity technique to solve and describe the request of shared resource from a program. The technique uses the cache analysis result based on abstract interpretation as inputs. It describes the maximum request of shared resource from a program in one unit time with a step function, which accurately describes the behavior of accessing shared resource. Based on this function, the thesis also proposes a WCRT analysis method. We assume that there is one real-time task in every processor core, and all the real-time tasks share bus, where accessing conflict may happen. The WCRT analysis method can iteratively compute execution overlap time of different tasks. According to the overlap case, the method can obtain the number of conflict times from other tasks on the shared bus in the worst case, and then the WCRT of every real-time task is obtained.To verify our WCRT analysis method, this thesis designs an experiment. Experimental results show that our approach is more precise than the task’s WCET gained by considering the worst case interferences with other tasks.
Keywords/Search Tags:WCRT, multicore real-time system, shared bus, access curve
PDF Full Text Request
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