Research On Communication Techniques Based On Shared Memory And Networks-on-chip On Multicore Architectures

With the development of integrated circuit manufacturing technology, more and more cores will be integrated on a signle chip to offer high-computing-capacity and low-power-consumption for embedded systems. Nowadays, the multicore technology has been playing an important role on mainstream applications. With the emergence of multicore systems, there are also some issues need to be solved, one of which is communication techniques. Data transfer and synchronization between multicores are implemented using communication. If the development of communication techniques doesn’t meet the requirement of communications for multicore systems, the performance of overall system will be limited by communication performance and can not be efficiently used. Therefore communication techniques are highly important for multicore systems.There are two kinds of communication structures in multicore system architectures. One is the shared memory communication. The architecture of reconfigurable systems is flexible and can be used to research communication techniques of multicore systems in depth. So, this dissertation researches the shared memory communication based on reconfigurable systems. And another communication structure is on-chip interconnect, which consistes of bus, crossbar, networks-on-chip. Networks-on-chip is more appropriate for multicore systems than other on-chip interconnects. For on-chip interconnects, this dissertation only researches networks-on-chip.This dissertation studies the high-performance and real-time communication based on these two communication structures. For the shared memory communication, proposing two communication solutions. For the on-chip interconnect, the dissertation proposes a mapping algorithm, which improves communication performance between NoC chips and off-chip memories, and two real-time scheduling algorithms for NoC. To be specific, the dissertation contributes in the following points:(1) The dissertation studies the shared memory communication mechanism in Impulse C. Impulse C is a high-level language widely used in the software/hardware codesign of reconfigurable systems and provides users with varies communication mechanisms. But the communication mechanisms of Impulse C are mainly designed for versatility and the resources within the FPGA chip is not fully utilized. In this dissertation, we present an improved implementation of the shared memory communication in Impulse C by utilizing both port of the dual-port BRAM. Experiment results show that the improved implementation can greatly improve the performance of shared memory communication, and further improve the execution efficiency of overall system.(2) The dissertation studies the shared memory communication mechanism in reconfigurable systems. A new communication mechanism based on virtual memorys for hardware tasks is introduced, and a hardware model is used to implement the behavior of memory management units, which makes hardware tasks communication in virtual memorys. This kind of mechanism is used to fulfill the communication of hardware tasks.(3) The dissertation studies the communication performance between NoC chips and off-chip memories. The communication performance between NoC chips and off-chip memories is low, which seriously limits the overall system performance. In this dissertation, we present a memory access aware mapping algorithm for NoC, which explores SDRAM access parallelization in order to offer higher off-chip memory communication efficiency, and eventually achieve higher overall system performance. Experimental results showed that, comparing with classical NoC mapping algorithms, our algorithm can significantly improve the memory utilization and overall system throughput.(4) The dissertation studies the real-time scheduling problem of cyclic communication sets in NoC. We propose two real time scheduling algorithms (CS-TI and CS-VC) for cyclic communication set and analyze the sufficient schedulability conditions of these two algorithms. We compare our algorithms with the existing fixed-priority algorithm which is the state of the art. Experimental results show that the acceptance rates of our algorithms are higher than that of the fixed-priority algorithm.(5) The dissertation studies the deadline assignment problem of end-to-end tasks in NoC. We develop three heuristic algorithms to determine the deadline of each subtask to guarantee the real-time performance of end to end tasks. We compare our algorithms with the classical proportional deadline algorithm. Experimental results show that the acceptance rates of our algorithms are higher than that of proportional deadline algorithm.To sum up, the dissertation studies the shared memory communication mechanism for reconfigurable systems. And high-performance and real-time communication in NoC are also explored. The work of this dissertation could provide reference value to designs for communication in multicore systems...