WCET Analysis Of Multicore Real-Time Systems With Shared Buses

It is predicted that multicore processors will be increasingly used in future embedded real-time systems for high performance and low energy consumption. The major obstacle is that people may not predict and provide any precise guarantee on real-time properties of the multicore real-time systems because of the shared resources. The shared memory bus is one of the most critical resources in the multicore systems, because all the cores can access the off-chip memory only with the shared bus. But at the same time, the shared bus may severely degrade the timing predictability of the multicore real-time systems. This is because that the bus delay for each core may not be precisely predicted due to the access contention between some cores.To solve this above problem, this thesis mainly analyzes the WCET of the multicore real-time system with the shared buses using the model checking technique. This thesis studies a multicore system model where each core has a private cache and all cores use a shared bus to access the off-chip memory. For the WCET analysis of the system model, this thesis firstly uses abstract interpretation technique to analyze the private instruction cache behavior of a program running on a dedicated core. After that, we can obtain the information whether each instruction of the program is in the instruction Cache or not. Based on these cache analysis results, this thesis then can construct a timed automaton for each program running in this multicore system with the help of UPPAAL model checker. These automatons of the programs can model the precise timing information on when to access the memory bus for each core. The thesis also models the behavior of the shared bus in the multicore system using a UPPAAL’s timed automaton. Finally, this thesis uses UPPAAL to check the whole system model composed of the automatons of the programs and the shared bus. With this method, it can obtain the precise WCET estimation of each program running in this multicore system with the shared bus.Based on the presented techniques, this thesis has developed a tool for analyzing the WCET of the multicore real-time system with the shared bus. This tool can automatically generate the timed automatons for the program and the bus respectively, and analyze the WCET estimation of one program running in this system. Using this tool, extensive experiments for the TDMA and FCFS buses have been conducted in this thesis. These experiment results show that the WCET analysis approach presented in this thesis can significantly tighten the WCET estimations. In both cases, the WCET estimations can be tightened by up to240%and82%respectively, compared with the worst-case bounds estimated based on cache misses and maximal delays for the bus access.