Analysis And Design Of A Fourth Order Bandpass Sigma-Delta Modulator

The bandpass sigma-delta modulator(BP DSM, for short) is the key block of the digital IF receiver. It digitizes the analog signal at an intermediate frequency, together with the digital decimation filter. Thus, the channel election and I/Q demodulation are operated in the digital domain. Then, the flexibility of the receiver is increased, and the complexity of the circuits-designing are relieved. So the bandpass sigma-delta modulator becomes one research focus in the field of RF communication. With the 0.18μm CMOS technology, this paper analyzes and designs a fourth order bandpass sigma-delta modulator.Firstly, the theory and basic structure of sigma-delta modulator are introduced, and the system scheme of a fourth order one bit single-loop multi-feedback is brought forward. Then the behavior model and functionality validation is done in the environment of MATLAB/SIMULINK with the SDToolbox. The simulation results show that the peak SNR arrives 95dB, satisfying the requirement. Besides, the behavior model points out the specifications of the main blocks, providing reference for circuit-level designing.Then, the fourth order BP DSM is designed at circuit-level, with the TSMC0.18 technology and operates with a 1.8V supply voltage. It main consists of the operational amplifier, DD(double-delay) resonator, 1bit quantizer, delay feedback and 1bit DAC, clock signal generation circuit and bandgap reference circuit. The center frequency is 20MHz, the OSR is 200, the bandwidth is 200kHz,and the sampling frequency is 80MHz. The simulation results show that the SNR arrives 84.2dB i.e. the effective number of bit is 14bit, and the static power of the system is 18mW.Finally, biasing the circuit-level designing, the layout of the BP DSM is accomplished and the post-simulation is done. The effective area is 0.7*0.4mm2, and the post-simulation shows the SNR is 75dB.