Front-end Design Of The Authentication Chip Based On RSA Algorithm For Electronic Systems

Recently, with the development of the hacking technology and chip anatomytechnology, the phenomenon that the electronic systems are copied is emerging.There is even the phenomenon that the number of imitation products is much morethan that of proprietary products. Therefore, the product designers are now faced withthe problem how to protect their own property. Based on this, in this thesis theauthentication chip for electronic systems is designed to protect the property rights ofelectronic systems by the hardware.The designed authentication chip for electronic systems is essentially a decryptionchip based on I2C bus protocol and RSA algorithm. To achieve the purpose of theprotection of electronic systems, the authentication chip is embedded in the electronichardware and the application software controls the program flow through randomauthentication with the authentication chip.The designed authentication chip mainly contains I2C interface module,1024-bitRSA decryption algorithm module, the read control module for Mask ROM IP Coreand so on.1024-bit RSA decryption algorithm module is the core module of the chip.The core of RSA algorithm is the modular exponentiation operation of large integerwhich can be decomposed into a series of modular multiplication operation. In thisthesis, the binary method which scans the bits of the key is used to decompose themodular exponentiation operation into a series of modular multiplication operation.The binary method scans the bits of the key either from left to right or from right toleft. The two types had been both realized and compared. In the operating frequencyof44MHz, the chip based on the left to right binary method achieves the decryptionrate of about28times per second and the one based on the right to left binary methodachieves the decryption rate of about42times per second. However, the area of thelatter chip is1.6times that of the former. By comparing, it is concluded that the leftto right binary method is based on area optimization and the right to left binarymethod is based on speed optimization. The modular multiplication module in thisthesis is based on Montgomery algorithm. By analyzing the algorithm deeply, thethesis has taken replacing subtraction–radix2Montgomery algorithm with the CSA(Carry Save Adder) and CLA (Carry Lookahead Adder) as the hardware implementation method of modular multiplication algorithm.The RTL-level description and testbench of the chip in Verilog HDL werecompleted. The simulation results proved that the RSA decryption module can realizefunction. Then the coding and logic synthesis were realized with Synopsys’s DesignCompiler and SMIC0.18μm CMOS process library and at the same time the scanchain for DFT was successfully inserted with the fault coverage of99.72%. Finally,the netlist with correct simulation results was obtained and the scan chain can beidentified correctly in Soc Encounter (one of the layout tools).