The Functional Verification Of A DSP Chip’s SOC Bus

Two different SOC bus plans are given in this paper by comparing two kinds of AMBA bus protocols-AHB bus protocol and AXI bus protocol. The plans are verified to ensure that the SOC bus can transmit information correctly through the core, the DMA, the peripheral groups, the external memory and the L2memory. And the configuration of the SOC bus’s arbitration by the system registers must be supported. At the same time, it should be ensured that the bus can support all types of data transfers between the function modules. What should be also ensured is the signals can transmit through different clock domains correctly. And it must be ensured that the transfer delay meets the design requirement.The SOC bus is formed with IP cores. So the IP cores must be verified before the functional verification of the SOC bus. The IP modules of the AHB bus mainly contain the AHB bus module, the AHB bus bridge module (eh2h and h2h) and the AHB bus interconnection module. The AHB bus module completes the data transfers from Master to Slave. The verification result of this module indicates that the function and transfer delay meets the design requirement. The AHB bus bridge module completes the data transfers between two buses. And it can complete the data transfers through different clock domains. There are two kinds of AHB bus bridge module-eh2h and h2h. The eh2h bus bridge contains a FIFO. The verification result of this module indicates that the transfer delay is large. But the burst transfers are supported. The h2h bus bridge doesn’t contain a FIFO. The verification result of this module indicates that the transfer delay is small. But the burst transfers are not supported. Only one-by-one transfers are supported. The AHB bus interconnection module completes the arbitration of accessing to the same destination from different buses. The verification result of this module indicates that the function and transfer delay meets the design requirement. The IP modules of the AXI bus mainly contain the AXI bus module and the AXI bus bridge module. The AXI bus module completes the data transfers from Master to Slave. And the AXI bus bridge module completes the data transfers between two buses. The functional verification result of the IP modules of the AXI bus indicates that the function and transfer delay meets the design requirement.Two kinds of SOC bus are constructed based on the two bus protocols in this paper. One kind of SOC bus is constructed entirely by the AHB bus protocol. This kind of SOC bus uses the AHB signals on both the Master and Slave ports. And it is constructed entirely by the IP modules of the AHB bus. For this kind of SOC bus, the core bus, the DMA bus and the PAB bus are selected for functional verification. The verification result of these buses indicates that the function meets the design requirement, but the transfer delay is too large to meet the design requirement. Another kind of SOC bus is constructed by the AHB bus protocol and the AXI bus protocol together. This kind of SOC bus uses the AXI signals on the Master port, and it uses the AHB signals on the Slave port. For this kind of SOC bus, the core bus, the DMA bus and the PAB bus are selected for functional verification. The verification result of this bus indicates that the function and transfer delay meets the design requirement.