Design And Realization Of Link-layer Chips Based On IEEE1394a Protocol

In today’s information society, with the wide application of computers andelectronic products, the highly efficient information processing characterized byhigh-speed, stable and timely data transmission has become increasingly demanding.IEEE1394bus protocol is a data transmission standard, it has the advantages of hightransmission rate, good scalability, high bandwidth capabilities, plug and play, and soon. IEEE l394bus can achieve data transmission between the point and the point, whichhas been widely used in audio and video direction, especially in the field of high-speeddevice interface. Meanwhile, the use of IEEE l394bus in test equipments andinterconnection networks has also been more and more attention.Since its customization, IEEE1394bus protocol has developed for20years andnow has also been widely used in various fields. The study of its application design inour country is relatively mature, but the research of core chip just starts and a long timeexploration is needed. Here, the main work is to design and verify a separate link layerchip with a strong compatibility, and can be connected to other embedded processorsand other chips.Based on the IEEE1394a serial bus protocol, the work give a brief introduction toits technical superiority and architecture and a main describe of the composition andfunction of the link layer. Focus is on the behavior design of the link layer chip, and thefunction verification of link layer from the perspective of physical layer/link layerinterface (PHY/Link interface). Starting with the IEEE1394a protocol, the functionalspecification and system architecture of link layer chip is established, the logic design ismainly processed followed by corresponding simulation of the function and timing, andthen the transmitting and receiving of the various types of data packets are realized. Theobtained timing simulation waveforms is in good agreement with the provisions of thestandard link-layer model, which illustrates the design feasibility of the greatly valuedlink layer chips and make a contribution to the development of relevant1394chips.