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Based On The FPGA2D Graphics Acceleration Design And Implementation

Posted on:2014-11-01Degree:MasterType:Thesis
Country:ChinaCandidate:C LiuFull Text:PDF
GTID:2298330431959699Subject:Software engineering
Abstract/Summary:PDF Full Text Request
Today, as everyone knows, science and technology are the core competitiveness.Studying of high performance graphics display technology and developing highperformance graphics accelerating engine system and technology to meet theapplication demand, has become the core and strategic location of our nationaldefense and modern development. Therefore, vigorously carry out the key computergraphics technology research, independent innovation, develop a completelyindependent intellectual property rights of the standardization and seriation ofhigh-end graphics technology products, has a strategic significance.This paper focuses on the two-dimensional graphics acceleration algorithmdesign and implementation. We analyze the history, status and the present situation athome and abroad of graphics acceleration, which indicate the significance andnecessity of the research and determine the direction and position the research. We dosome exploratory research in two dimensional graphics acceleration principle, theoverall system architecture, graphic algorithm architecture, hardware architecture,collaborative design of hardware and software, system integration design, realizationand the functional verification and performance evaluation etc. aspects based onSOPC reconfigurable hardware platform and FPGA single chip.The simulation and experimental results verify that the design andimplementation of the subject greatly improve the graphics accelerating function of2D graphics generation, realize two-dimensional graphics acceleration system whichbasically meet function and the performance requirements of the airborneenvironment, developed the2D graphics acceleration systems and technologies.withfull independent intellectual property rights.
Keywords/Search Tags:Graphics acceleration engine, Primitive algorithm architecture, Hardware bus transfer, FPGA
PDF Full Text Request
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