Design Of 14Gb/s Single-channel Optical Fiber Data Transmission ASIC For High Energy Physics Experiment

High-energy physics experiment is a basic experiment to explore and study the characteristics of high-energy collision particles,strong radiation environment and massive data information brought by tens of millions of particle collisions per second in the experiment brought severe challenges to the design of front-end electronics data transmission system of the detector.Optical communication technology has gradually become the mainstream technology choice for front-end data transmission of detectors due to its fast transmission rate,high stability,and strong anti-interference ability,the optical fiber data transmission chip with the advantages of high integration,high bandwidth and strong radiation resistance is the core component in the optical communication system.However,the optical fiber data transmission chips currently on the market do not have the ability to resist radiation,and such chips are almost monopolized by foreign countries,and the domestic long-term embargo,so it is extremely urgent to research and develop optical fiber data transmission chips that can meet the above requirements.The main research work of this paper is to develop a 14Gb/s single-channel optical fiber data transmission chip against the background of strong radiation and high density data transmission.The chip sets the driver and receiver module in one,and cooperates with TOSA(Transmitter Optical Subassembly)and ROSA(Receiver Optical Subassembly)to realize the conversion of optical-electrical signals,it aims to solve the problem of high-speed transmission of data from front-end detectors in high-energy physics experiments.Its specific research content and innovations are reflected in the following aspects:1.In the module of optical driver:the output driver stage adopts a novel structure of capacitive coupling pre-emphasis,which realizes the pre-emphasis effect,reduces the attenuation of high-frequency signals caused by parasitic parameters,improves the quality of the output eye diagram,and makes up for the shortcomings of the traditional pre-emphasis circuit to obtain pre-emphasis at the expense of low-frequency gain.The post-simulation results show that with a 14 Gb/s PRBS7 signal with a differential input of 200 mV,when the output eye current is 2 mA～7 mA,the eye jitter is 4.14 ps.2.In the design of the optical receiver module:the output buffer stage adopts the shared inductance technology and pre-emphasis technology of the CTLE structure,which improves the analog bandwidth and improves the quality of the eye diagram.The post-simulation results show that the AC analog bandwidth is increased by about 2 GHz at TT 27℃.When the input differential 200mV,14Gb/s PRBS7 signal and the output differential voltage amplitude are 740mV,the jitter of the transient eye diagram is 3.45ps.3.In the design of optical driver and optical receiver modules:the input stage uses a CTLE structured equalization circuit to compensate for high-frequency signal attenuation caused by parasitic parameters such as transmission lines,bonding lines,and input PAD,different equalization gears are designed to deal with uncertain measured environments and improve the signal bandwidth;The shared inductance structure is used in the limiting amplifier stage,compared with the parallel inductance structure,the area is reduced,the bandwidth is further improved,and the active feedback circuit is introduced to overcome the gain and bandwidth fluctuation under different process corners and temperature combinations.4.In the optimization of the anti-radiation performance of the chip:the chip adopts the SMIC 55nm RF CMOS domestic technology and uses a single finger wider MOS tube design,which reduces the effect of the Total Ionizing Dose(TID)and realizes the radiation reinforcement of the analog circuit;The digital I2C module adopts a three-mode redundant circuit topology,which overcomes the Single Event Upset(SEU)and realizes the radiation reinforcement of the digital logic circuit.At present,the chip has been designed,the overall area:1666um×1545um,including 36 PAD;and complete post-simulation,the results show that under the input differential 200mV,14Gb/s PRBS7 signal,the jitter of the output eye diagram of the optical driver and optical receiver module is 4.14ps and 3.45ps,and the total power consumption of the chip is less than 90mW,achieved the expected goal;The chip GDS has been generated and is ready to be handed over to the foundry,the next step will be to arrange chip taping and actual measurement.