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Design Of Real-Time Image Noise Reduction System Based On FPGA

Posted on:2010-06-01Degree:MasterType:Thesis
Country:ChinaCandidate:X M KongFull Text:PDF
GTID:2178360278457840Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Image information in the mainstream of everyday life has emerged, which has become the human acquired one of the most important information. However, the image signal interfers all kinds of noise in the the process of generation, transmission and recording, the adoption of appropriate ways to reduce noise is a very important pre-treatment process. With the rapid development of microelectronic technology, FPGA hardware has become the treatment of real-time image data of an ideal choice, image processing research based on FPGA will become a new hot spot for the information industry.This article firstly analyzes the status of image denoising deal, compares the advantages and disadvantages of FPGA, DSP and ASIC chip, and combines with the design of the background and needs to give the overall treatment program that is the real time image noise reduction system based on FPGA. Each peripheral interface control logic, chip control logic, algorithm processing module in the program depend on the FPGA implementation, they became a simple scalable SOC system, with implementation of video acquisition, image pre-processing function of FPGA subsystem. The system uses Altera's FPGA chip as the CPU, the system has the image acquisition module, asynchronous FIFO module, image frame memory control module, and image handle low-level module. One of OV9121 image sensor under the control of the FPGA is responsible for image acquisition, two SDRAMs are video images of the cache, sampling control and filtering algorithm implemet in the FPGA.The algorithms of image processing takes into account the real time performance, algorithm complexity and other factors, the design selects the improved median filtering algorithm as the noise reduction algorithm. Firstly algorithm implementation uses 3×3 cross-shaped form module to replace the commonly 3×3 square form module; the design takes FPGA with the characteristics of parallel processing, the bubble sort parallel algorithm is taken the place of the odd-even sorting algorithm using VHDL to complete the program and making algorithm in hardware and software programmers promoted.This article includes image acquisition part OV9121 module initialization, sample control module and control module SDRAM. Initialization module is based mainly on the design requirements, setting the OV9121 mode, image resolution, frame rate and other parameters; sampling control module mainly provides acquisition of the necessary control signals; SDRAM control module is mainly responsible for output image data and senting image data to filter module. The entire design and each module had been designed with the chip EP1C6Q240C8 which is made in Altera Corporation Cyclones. The logic synthesis and simulation had finished in the company's Aletar development environment QuartusII 8.1. The results of the synthesis and simulation show that the use of FPGA hardware image data not only get good treatment results, reach a higher operating frequency, and processing speed is also much higher than the software method deal with images, can meet the requirements of real-time image processing.
Keywords/Search Tags:FPGA, VHDL, SOC, Median Filter Algorithm, Image Noise Reduction
PDF Full Text Request
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