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Design Of The Self-adaptive Audio Noise Reduction System Based On FPGA

Posted on:2016-07-02Degree:MasterType:Thesis
Country:ChinaCandidate:R Z PanFull Text:PDF
GTID:2308330464454607Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
During process of communication, the voice often get interfered by various noises, such as the ones made by running automobiles、watercraft and other mechanical equipment. These noise lead to low communication quality. In order to suppress the interference of noise and elevate the quality of communication, it is necessary to research on the noise reduction technology.The application of audio noise reduction technology in the mobile terminal is very extensive, like the technology used in HUAWEI C8800 and SAMSUNG i9100 etc. Most these technologies are realized on the serial arithmetic ARM platform, the realization of noise reduction algorithm occupies too many time slices of CPU, and it can only deal with the low sampling rates of data stream. There are also some specialized chips can reduce noise, but it would increase the cost and enlarge the PCB area. AS such problems are concerned, this paper designs a Self-adaptive Audio Noise Reduction System based on FPGA.Firstly, this paper researched The LMS algorithm in Self-adaptive noise reduction. Secondly, the Self-adaptive Audio Noise Reduction System is designed with LMS algorithm as its core and FPGA as its platform. Last, the performance of the system is tested, and a few things need to improve are found out. The major works are as follows:(1) The application of LMS algorithm in audio noise reduction is researched, and its performance is tested via simulation on MATLAB platform.(2) Self-adaptive Audio Noise Reduction System is structured with DE2 and EZ-USB as its hardware platform. The peripheral circuits are, designed for USB Microcontroller and audio processing chip.(3) Verilog Language programming is completed for Audio Data Collection Module、 Self-adaptive Noise Reduction Module and SRAM Cache Module in FPGA chip.(4) USB Microcontroller Firmware、USB Data Sending Interface and Upper Monitor Audio reception software are designed, making the USB2.0 audio data transmission between FPGA and upper monitor happen.(5) The performance of Self-adaptive Audio Noise Reduction System is tested via the simulation on Modelsim and experimented in real environments.From all above, this paper completes the Self-adaptive Audio Noise Reduction System by software and hardware design. The configure of relevant register、the key design of each module and the design cycle of every program are given in this paper, making the paper of great reference value.
Keywords/Search Tags:Audio Noise Reduction, Field-Programmable Gate Array, LMS Algorithm, USB2.0
PDF Full Text Request
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