Discrete Hilbert Transform Design And Implementation For The Cone-beam CT With FPGA

Spiral cone-beam CT (Computed Tomography) scanning surface reconstructiontechnique has the advantages of high sweep speed and high spatial resolution, whichgains more and more attention. But the spiral cone-beam CT reconstruction theory ismore complex and the amount of calculation is very large, so the reconstruction speed isthe bottleneck of this theory. Because of a huge amount of data traffic and computation，cone-beam CT reconstruction just relying on the software to complete thereconstruction task has been unable to meet the needs of medicine and engineering.Three-dimensional image reconstruction task, completed by software and hardware, cangreatly reduce CPU burden and improve the rate of image reconstruction, so theresearch of cone-beam CT image reconstruction speed has high application value andresearch value. In this dissertation, discrete Hilbert transform (DHT) part of cone-beamCT image reconstruction has been studied in detail, and the DHT hardware accelerationsystem has been proposed and implemented. The hardware circuits have used parallelstructure, so that1024points DHT computation time is56us.The data format hasselected single-precision floating-point data structure and the operation precision ofDHT hardware circuit is10-5. This study includes four parts:Firstly, in this dissertation, it is proposed that FFT is choosed as the way toimplement DHT after comparing the speed and area of several implementation ways ofDHT. Secondly, the DHT butterfly flowchart is designed and the hardware circuit ofDHT implementation is designed according to the butterfly flowchart. Thirdly, thehardware circuit of DHT with the single-precision floating-point adder and multiplier ofFPGA IP core is implemented. The hardware circuit of DHT has goodperformance.Fourthly, the DHT hardware circuit was improved so that DHT hardwarecircuit interfaces is fully fit for the PCIE bus interfaces and cone-beam CT imagereconstruction DHT hardware acceleration is achieved in Xilinx’s XC5VLX50T FPGAdevices ML555development board with PCIE bus. Matlab are used to do a calculationresult of FPGA verification interface DHT and verifie the correctness of DHT hardwareacceleration system.In this dessertation, the DHT FPGA hardware circuit performance is comparedwith the other structures of the the literature, and the time of computing a time DHT isless58us than Altera IP core. The DHT FPGA hardware has a good real-time. Thefunction that the DHT hardware circuit is controlled by PC in this DHT hardwareacceleration system is a solid foundation to achieve cone-beam CT image reconstructiontask with the software and hardware together.